xref: /openbmc/u-boot/include/configs/at91rm9200ek.h (revision 8343f8a76434b7162cf5a4da5f456b014868853c)
1 /*
2  * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
3  *
4  * based on previous work by
5  *
6  * Ulf Samuelsson <ulf@atmel.com>
7  * Rick Bronson <rick@efn.org>
8  *
9  * Configuration settings for the AT91RM9200EK board.
10  *
11  * See file CREDITS for list of people who contributed to this
12  * project.
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License as
16  * published by the Free Software Foundation; either version 2 of
17  * the License, or (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27  * MA 02111-1307 USA
28  */
29 
30 #ifndef __AT91RM9200EK_CONFIG_H__
31 #define __AT91RM9200EK_CONFIG_H__
32 
33 #include <asm/sizes.h>
34 
35 /*
36  * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
37  * AT91C_MAIN_CLOCK is the frequency of PLLA output
38  * AT91C_MASTER_CLOCK is the peripherial clock
39  * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
40  *  set in arch/arm/cpu/arm920t/at91/timer.c)
41  * CONFIG_SYS_HZ is the tick rate for timer tc0
42  */
43 #define AT91C_XTAL_CLOCK		18432000
44 #define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
45 #define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3 )
46 #define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
47 #define CONFIG_SYS_HZ			1000
48 
49 /* CPU configuration */
50 #define CONFIG_ARM920T
51 #define CONFIG_AT91RM9200
52 #define CONFIG_AT91RM9200EK
53 #define CONFIG_CPUAT91
54 #define USE_920T_MMU
55 
56 #define CONFIG_CMDLINE_TAG
57 #define CONFIG_SETUP_MEMORY_TAGS
58 #define CONFIG_INITRD_TAG
59 
60 /*
61  * Memory Configuration
62  */
63 #define CONFIG_NR_DRAM_BANKS		1
64 #define CONFIG_SYS_SDRAM_BASE		0x20000000
65 #define CONFIG_SYS_SDRAM_SIZE		SZ_32M
66 
67 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
68 #define CONFIG_SYS_MEMTEST_END		\
69 		(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
70 
71 /*
72  * LowLevel Init
73  */
74 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
75 #define CONFIG_SYS_USE_MAIN_OSCILLATOR
76 /* flash */
77 #define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
78 #define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
79 
80 /* clocks */
81 #define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
82 #define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
83 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
84 #define CONFIG_SYS_MCKR_VAL	0x00000202
85 
86 /* sdram */
87 #define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
88 #define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
89 #define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
90 #define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
91 #define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
92 #define CONFIG_SYS_SDRAM	CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
93 #define CONFIG_SYS_SDRAM1	CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
94 #define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
95 #define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
96 #define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
97 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
98 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
99 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
100 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
101 
102 /*
103  * Hardware drivers
104  */
105 /*
106  * Choose a USART for serial console
107  * CONFIG_DBGU is DBGU unit on J10
108  * CONFIG_USART1 is USART1 on J14
109  */
110 #define CONFIG_AT91RM9200_USART
111 #define CONFIG_DBGU
112 
113 #define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
114 #define CONFIG_BAUDRATE			115200
115 
116 /*
117  * Command line configuration.
118  */
119 #include <config_cmd_default.h>
120 
121 #define CONFIG_CMD_DHCP
122 #define CONFIG_CMD_FAT
123 #define CONFIG_CMD_MII
124 #define CONFIG_CMD_PING
125 #define CONFIG_CMD_USB
126 #undef CONFIG_CMD_FPGA
127 
128 /*
129  * Network Driver Setting
130  */
131 #define CONFIG_NET_MULTI
132 #define CONFIG_DRIVER_AT91EMAC
133 #define CONFIG_SYS_RX_ETH_BUFFER	16
134 #define CONFIG_RMII
135 #define CONFIG_MII
136 
137 /*
138  * NOR Flash
139  */
140 #define CONFIG_FLASH_CFI_DRIVER
141 #define CONFIG_SYS_FLASH_CFI
142 #define CONFIG_SYS_FLASH_BASE		0x10000000
143 #define PHYS_FLASH_1			CONFIG_SYS_FLASH_BASE
144 #define PHYS_FLASH_SIZE			SZ_8M
145 #define CONFIG_SYS_MAX_FLASH_BANKS	1
146 #define CONFIG_SYS_MAX_FLASH_SECT	256
147 #define CONFIG_SYS_FLASH_PROTECTION
148 
149 /*
150  * USB Config
151  */
152 #define CONFIG_USB_ATMEL			1
153 #define CONFIG_USB_OHCI_NEW			1
154 #define CONFIG_USB_KEYBOARD			1
155 #define CONFIG_USB_STORAGE			1
156 #define CONFIG_DOS_PARTITION			1
157 
158 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
159 #define CONFIG_SYS_USB_OHCI_REGS_BASE		AT91_USB_HOST_BASE
160 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
161 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
162 
163 /*
164  * Environment Settings
165  */
166 #define CONFIG_ENV_IS_IN_FLASH
167 
168 /*
169  * after u-boot.bin
170  */
171 #define CONFIG_ENV_ADDR			\
172 		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
173 #define CONFIG_ENV_SIZE			SZ_64K /* sectors are 64K here */
174 /* The following #defines are needed to get flash environment right */
175 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
176 #define CONFIG_SYS_MONITOR_LEN		SZ_256K
177 
178 /*
179  * Boot option
180  */
181 #define CONFIG_BOOTDELAY		3
182 
183 /* default load address */
184 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_16M
185 #define CONFIG_ENV_OVERWRITE
186 
187 /*
188  * Shell Settings
189  */
190 #define CONFIG_CMDLINE_EDITING
191 #define CONFIG_SYS_LONGHELP
192 #define CONFIG_AUTO_COMPLETE
193 #define CONFIG_SYS_HUSH_PARSER
194 #define CONFIG_SYS_PROMPT		"U-Boot> "
195 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
196 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
197 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
198 /* Print Buffer Size */
199 #define CONFIG_SYS_PBSIZE		\
200 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
201 
202 /*
203  * Size of malloc() pool
204  */
205 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
206 					     SZ_4K)
207 /* size in bytes reserved for initial data */
208 
209 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
210 					- GENERATED_GBL_DATA_SIZE)
211 
212 #define CONFIG_STACKSIZE		SZ_32K	/* regular stack */
213 #define CONFIG_STACKSIZE_IRQ		SZ_4K	/* Unsure if to big or to small*/
214 #define CONFIG_STACKSIZE_FIQ		SZ_4K	/* Unsure if to big or to small*/
215 #endif /* __AT91RM9200EK_CONFIG_H__ */
216