1 /* 2 * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com> 3 * 4 * based on previous work by 5 * 6 * Ulf Samuelsson <ulf@atmel.com> 7 * Rick Bronson <rick@efn.org> 8 * 9 * Configuration settings for the AT91RM9200EK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #ifndef __AT91RM9200EK_CONFIG_H__ 31 #define __AT91RM9200EK_CONFIG_H__ 32 33 #include <asm/sizes.h> 34 35 /* 36 * set some initial configurations depending on configure target 37 * 38 * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0 39 * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel 40 * initialisation was done by some preloader 41 */ 42 #ifdef CONFIG_RAMBOOT 43 #define CONFIG_SKIP_LOWLEVEL_INIT 44 #define CONFIG_SYS_TEXT_BASE 0x20100000 45 #else 46 #define CONFIG_SYS_TEXT_BASE 0x10000000 47 #endif 48 49 /* 50 * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz 51 * AT91C_MAIN_CLOCK is the frequency of PLLA output 52 * AT91C_MASTER_CLOCK is the peripherial clock 53 * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely 54 * set in arch/arm/cpu/arm920t/at91/timer.c) 55 * CONFIG_SYS_HZ is the tick rate for timer tc0 56 */ 57 #define AT91C_XTAL_CLOCK 18432000 58 #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) 59 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) 60 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) 61 #define CONFIG_SYS_HZ 1000 62 63 /* CPU configuration */ 64 #define CONFIG_ARM920T 65 #define CONFIG_AT91RM9200 66 #define CONFIG_AT91RM9200EK 67 #define CONFIG_CPUAT91 68 #define USE_920T_MMU 69 70 #define CONFIG_CMDLINE_TAG 71 #define CONFIG_SETUP_MEMORY_TAGS 72 #define CONFIG_INITRD_TAG 73 74 #define CONFIG_AT91FAMILY 75 76 /* 77 * Memory Configuration 78 */ 79 #define CONFIG_NR_DRAM_BANKS 1 80 #define CONFIG_SYS_SDRAM_BASE 0x20000000 81 #define CONFIG_SYS_SDRAM_SIZE SZ_32M 82 83 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 84 #define CONFIG_SYS_MEMTEST_END \ 85 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K) 86 87 /* 88 * LowLevel Init 89 */ 90 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 91 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 92 /* flash */ 93 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 94 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ 95 96 /* clocks */ 97 #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ 98 #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ 99 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ 100 #define CONFIG_SYS_MCKR_VAL 0x00000202 101 102 /* sdram */ 103 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ 104 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 105 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 106 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ 107 #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ 108 #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ 109 #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80) 110 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ 111 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ 112 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ 113 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ 114 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ 115 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ 116 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 117 118 /* 119 * Hardware drivers 120 */ 121 /* 122 * Choose a USART for serial console 123 * CONFIG_DBGU is DBGU unit on J10 124 * CONFIG_USART1 is USART1 on J14 125 */ 126 #define CONFIG_AT91RM9200_USART 127 #define CONFIG_DBGU 128 129 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 130 #define CONFIG_BAUDRATE 115200 131 132 /* 133 * Command line configuration. 134 */ 135 #include <config_cmd_default.h> 136 137 #define CONFIG_CMD_DHCP 138 #define CONFIG_CMD_FAT 139 #define CONFIG_CMD_MII 140 #define CONFIG_CMD_PING 141 #define CONFIG_CMD_USB 142 #undef CONFIG_CMD_FPGA 143 144 /* 145 * Network Driver Setting 146 */ 147 #define CONFIG_NET_MULTI 148 #define CONFIG_DRIVER_AT91EMAC 149 #define CONFIG_SYS_RX_ETH_BUFFER 16 150 #define CONFIG_RMII 151 #define CONFIG_MII 152 153 /* 154 * NOR Flash 155 */ 156 #define CONFIG_FLASH_CFI_DRIVER 157 #define CONFIG_SYS_FLASH_CFI 158 #define CONFIG_SYS_FLASH_BASE 0x10000000 159 #define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE 160 #define PHYS_FLASH_SIZE SZ_8M 161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 162 #define CONFIG_SYS_MAX_FLASH_SECT 256 163 #define CONFIG_SYS_FLASH_PROTECTION 164 165 /* 166 * USB Config 167 */ 168 #define CONFIG_USB_ATMEL 1 169 #define CONFIG_USB_OHCI_NEW 1 170 #define CONFIG_USB_KEYBOARD 1 171 #define CONFIG_USB_STORAGE 1 172 #define CONFIG_DOS_PARTITION 1 173 174 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 175 #define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE 176 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" 177 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 178 179 /* 180 * Environment Settings 181 */ 182 #define CONFIG_ENV_IS_IN_FLASH 183 184 /* 185 * after u-boot.bin 186 */ 187 #define CONFIG_ENV_ADDR \ 188 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 189 #define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */ 190 /* The following #defines are needed to get flash environment right */ 191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 192 #define CONFIG_SYS_MONITOR_LEN SZ_256K 193 194 /* 195 * Boot option 196 */ 197 #define CONFIG_BOOTDELAY 3 198 199 /* default load address */ 200 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M 201 #define CONFIG_ENV_OVERWRITE 202 203 /* 204 * Shell Settings 205 */ 206 #define CONFIG_CMDLINE_EDITING 207 #define CONFIG_SYS_LONGHELP 208 #define CONFIG_AUTO_COMPLETE 209 #define CONFIG_SYS_HUSH_PARSER 210 #define CONFIG_SYS_PROMPT "U-Boot> " 211 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 212 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 213 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 214 /* Print Buffer Size */ 215 #define CONFIG_SYS_PBSIZE \ 216 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 217 218 /* 219 * Size of malloc() pool 220 */ 221 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \ 222 SZ_4K) 223 /* size in bytes reserved for initial data */ 224 225 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ 226 - GENERATED_GBL_DATA_SIZE) 227 228 #define CONFIG_STACKSIZE SZ_32K /* regular stack */ 229 #define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/ 230 #define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/ 231 #endif /* __AT91RM9200EK_CONFIG_H__ */ 232