1 /*
2  * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
3  *
4  * based on previous work by
5  *
6  * Ulf Samuelsson <ulf@atmel.com>
7  * Rick Bronson <rick@efn.org>
8  *
9  * Configuration settings for the AT91RM9200EK board.
10  *
11  * SPDX-License-Identifier:	GPL-2.0+
12  */
13 
14 #ifndef __AT91RM9200EK_CONFIG_H__
15 #define __AT91RM9200EK_CONFIG_H__
16 
17 #include <linux/sizes.h>
18 
19 /*
20  * set some initial configurations depending on configure target
21  *
22  * at91rm9200ek_config     -> boot from 0x0 in NOR Flash at CS0
23  * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
24  *                            initialisation was done by some preloader
25  */
26 #ifdef CONFIG_RAMBOOT
27 #define CONFIG_SKIP_LOWLEVEL_INIT
28 #define CONFIG_SYS_TEXT_BASE 0x20100000
29 #else
30 #define CONFIG_SYS_TEXT_BASE 0x10000000
31 #endif
32 
33 /*
34  * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
35  * AT91C_MAIN_CLOCK is the frequency of PLLA output
36  * AT91C_MASTER_CLOCK is the peripherial clock
37  * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
38  *  set in arch/arm/cpu/arm920t/at91/timer.c)
39  * CONFIG_SYS_HZ is the tick rate for timer tc0
40  */
41 #define AT91C_XTAL_CLOCK		18432000
42 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
43 #define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
44 #define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3 )
45 #define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
46 
47 /* CPU configuration */
48 #define CONFIG_AT91RM9200
49 #define CONFIG_AT91RM9200EK
50 #define CONFIG_CPUAT91
51 #define USE_920T_MMU
52 
53 #include <asm/hardware.h>	/* needed for port definitions */
54 
55 #define CONFIG_CMDLINE_TAG
56 #define CONFIG_SETUP_MEMORY_TAGS
57 #define CONFIG_INITRD_TAG
58 
59 #define CONFIG_BOARD_EARLY_INIT_F
60 
61 #define CONFIG_CMD_BOOTZ
62 
63 
64 /*
65  * Memory Configuration
66  */
67 #define CONFIG_NR_DRAM_BANKS		1
68 #define CONFIG_SYS_SDRAM_BASE		0x20000000
69 #define CONFIG_SYS_SDRAM_SIZE		SZ_32M
70 
71 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
72 #define CONFIG_SYS_MEMTEST_END		\
73 		(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
74 
75 /*
76  * LowLevel Init
77  */
78 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
79 #define CONFIG_SYS_USE_MAIN_OSCILLATOR
80 /* flash */
81 #define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
82 #define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
83 
84 /* clocks */
85 #define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
86 #define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
87 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
88 #define CONFIG_SYS_MCKR_VAL	0x00000202
89 
90 /* sdram */
91 #define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
92 #define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
93 #define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
94 #define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
95 #define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
96 #define CONFIG_SYS_SDRAM	CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
97 #define CONFIG_SYS_SDRAM1	(CONFIG_SYS_SDRAM_BASE+0x80)
98 #define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
99 #define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
100 #define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
101 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
102 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
103 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
104 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
105 
106 /*
107  * Hardware drivers
108  */
109 /*
110  * Choose a USART for serial console
111  * CONFIG_DBGU is DBGU unit on J10
112  * CONFIG_USART1 is USART1 on J14
113  */
114 #define CONFIG_ATMEL_USART
115 #define CONFIG_USART_BASE	ATMEL_BASE_DBGU
116 #define CONFIG_USART_ID		0/* ignored in arm */
117 
118 #define CONFIG_BAUDRATE			115200
119 
120 /*
121  * Command line configuration.
122  */
123 #define CONFIG_CMD_DHCP
124 #define CONFIG_CMD_FAT
125 #define CONFIG_CMD_MII
126 #define CONFIG_CMD_PING
127 #define CONFIG_CMD_USB
128 
129 /*
130  * Network Driver Setting
131  */
132 #define CONFIG_DRIVER_AT91EMAC
133 #define CONFIG_SYS_RX_ETH_BUFFER	16
134 #define CONFIG_RMII
135 #define CONFIG_MII
136 
137 /*
138  * NOR Flash
139  */
140 #define CONFIG_FLASH_CFI_DRIVER
141 #define CONFIG_SYS_FLASH_CFI
142 #define CONFIG_SYS_FLASH_BASE		0x10000000
143 #define PHYS_FLASH_1			CONFIG_SYS_FLASH_BASE
144 #define PHYS_FLASH_SIZE			SZ_8M
145 #define CONFIG_SYS_MAX_FLASH_BANKS	1
146 #define CONFIG_SYS_MAX_FLASH_SECT	256
147 #define CONFIG_SYS_FLASH_PROTECTION
148 
149 /*
150  * USB Config
151  */
152 #define CONFIG_USB_ATMEL			1
153 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
154 #define CONFIG_USB_OHCI_NEW			1
155 #define CONFIG_USB_KEYBOARD			1
156 #define CONFIG_USB_STORAGE			1
157 #define CONFIG_DOS_PARTITION			1
158 
159 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
160 #define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_USB_HOST_BASE
161 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
162 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
163 
164 /*
165  * Environment Settings
166  */
167 #define CONFIG_ENV_IS_IN_FLASH
168 
169 /*
170  * after u-boot.bin
171  */
172 #define CONFIG_ENV_ADDR			\
173 		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
174 #define CONFIG_ENV_SIZE			SZ_64K /* sectors are 64K here */
175 /* The following #defines are needed to get flash environment right */
176 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
177 #define CONFIG_SYS_MONITOR_LEN		SZ_256K
178 
179 /*
180  * Boot option
181  */
182 #define CONFIG_BOOTDELAY		3
183 
184 /* default load address */
185 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_16M
186 #define CONFIG_ENV_OVERWRITE
187 
188 /*
189  * Shell Settings
190  */
191 #define CONFIG_CMDLINE_EDITING
192 #define CONFIG_SYS_LONGHELP
193 #define CONFIG_AUTO_COMPLETE
194 #define CONFIG_SYS_HUSH_PARSER
195 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
196 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
197 /* Print Buffer Size */
198 #define CONFIG_SYS_PBSIZE		\
199 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
200 
201 /*
202  * Size of malloc() pool
203  */
204 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
205 					     SZ_4K)
206 
207 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
208 					- GENERATED_GBL_DATA_SIZE)
209 
210 #endif /* __AT91RM9200EK_CONFIG_H__ */
211