1 /* 2 * Configuration settings for the Sentec Cobra Board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * configuration for ASTRO "Urmel" board. 11 * Originating from Cobra5272 configuration, messed up by 12 * Wolfgang Wegner <w.wegner@astro-kom.de> 13 * Please do not bother the original author with bug reports 14 * concerning this file. 15 */ 16 17 #ifndef _CONFIG_ASTRO_MCF5373L_H 18 #define _CONFIG_ASTRO_MCF5373L_H 19 20 #include <linux/stringify.h> 21 22 /* 23 * set the card type to actually compile for; either of 24 * the possibilities listed below has to be used! 25 */ 26 #define CONFIG_ASTRO_V532 1 27 28 #if CONFIG_ASTRO_V532 29 #define ASTRO_ID 0xF8 30 #elif CONFIG_ASTRO_V512 31 #define ASTRO_ID 0xFA 32 #elif CONFIG_ASTRO_TWIN7S2 33 #define ASTRO_ID 0xF9 34 #elif CONFIG_ASTRO_V912 35 #define ASTRO_ID 0xFC 36 #elif CONFIG_ASTRO_COFDMDUOS2 37 #define ASTRO_ID 0xFB 38 #else 39 #error No card type defined! 40 #endif 41 42 /* Command line configuration */ 43 /* 44 * CONFIG_RAM defines if u-boot is loaded via BDM (or started from 45 * a different bootloader that has already performed RAM setup) or 46 * started directly from flash, which is the regular case for production 47 * boards. 48 */ 49 #ifdef CONFIG_RAM 50 #define CONFIG_MONITOR_IS_IN_RAM 51 #define ENABLE_JFFS 0 52 #else 53 #define ENABLE_JFFS 1 54 #endif 55 56 #define CONFIG_CMDLINE_EDITING 57 58 #define CONFIG_MCFRTC 59 #undef RTC_DEBUG 60 61 /* Timer */ 62 #define CONFIG_MCFTMR 63 #undef CONFIG_MCFPIT 64 65 /* I2C */ 66 #define CONFIG_SYS_I2C 67 #define CONFIG_SYS_I2C_FSL 68 #define CONFIG_SYS_FSL_I2C_SPEED 80000 69 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 70 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 71 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 72 73 /* 74 * Defines processor clock - important for correct timings concerning serial 75 * interface etc. 76 */ 77 78 #define CONFIG_SYS_CLK 80000000 79 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) 80 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 81 82 #define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 83 #define CONFIG_SYS_CORE_SRAM 0x80000000 84 85 #define CONFIG_SYS_UNIFY_CACHE 86 87 /* 88 * Define baudrate for UART1 (console output, tftp, ...) 89 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud 90 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected 91 * in u-boot command interface 92 */ 93 94 #define CONFIG_MCFUART 95 #define CONFIG_SYS_UART_PORT (2) 96 #define CONFIG_SYS_UART2_ALT3_GPIO 97 98 /* 99 * Watchdog configuration; Watchdog is disabled for running from RAM 100 * and set to highest possible value else. Beware there is no check 101 * in the watchdog code to validate the timeout value set here! 102 */ 103 104 #ifndef CONFIG_MONITOR_IS_IN_RAM 105 #define CONFIG_WATCHDOG 106 #define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ 107 #endif 108 109 /* 110 * Configuration for environment 111 * Environment is located in the last sector of the flash 112 */ 113 114 #ifndef CONFIG_MONITOR_IS_IN_RAM 115 #define CONFIG_ENV_OFFSET 0x1FF8000 116 #define CONFIG_ENV_SECT_SIZE 0x8000 117 #else 118 /* 119 * environment in RAM - This is used to use a single PC-based application 120 * to load an image, load U-Boot, load an environment and then start U-Boot 121 * to execute the commands from the environment. Feedback is done via setting 122 * and reading memory locations. 123 */ 124 #define CONFIG_ENV_ADDR 0x40060000 125 #define CONFIG_ENV_SECT_SIZE 0x8000 126 #endif 127 128 /* here we put our FPGA configuration... */ 129 #define CONFIG_MISC_INIT_R 1 130 131 /* Define user parameters that have to be customized most likely */ 132 133 /* AUTOBOOT settings - booting images automatically by u-boot after power on */ 134 135 /* 136 * The following settings will be contained in the environment block ; if you 137 * want to use a neutral environment all those settings can be manually set in 138 * u-boot: 'set' command 139 */ 140 141 #define CONFIG_EXTRA_ENV_SETTINGS \ 142 "loaderversion=11\0" \ 143 "card_id="__stringify(ASTRO_ID)"\0" \ 144 "alterafile=0\0" \ 145 "xilinxfile=0\0" \ 146 "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ 147 "fpga load 0 0x41000000 $filesize\0" \ 148 "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ 149 "fpga load 1 0x41000000 $filesize\0" \ 150 "env_default=1\0" \ 151 "env_check=if test $env_default -eq 1;"\ 152 " then setenv env_default 0;saveenv;fi\0" 153 154 /* 155 * "update" is a non-standard command that has to be supplied 156 * by external update.c; This is not included in mainline because 157 * it needs non-blocking CFI routines. 158 */ 159 #ifdef CONFIG_MONITOR_IS_IN_RAM 160 #define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ 161 #else 162 #if CONFIG_ASTRO_V532 163 #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ 164 "run xilinxload&&run alteraload&&bootm 0x80000;"\ 165 "update;reset" 166 #else 167 #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ 168 "run xilinxload&&bootm 0x80000;update;reset" 169 #endif 170 #endif 171 172 /* default RAM address for user programs */ 173 #define CONFIG_SYS_LOAD_ADDR 0x20000 174 175 #define CONFIG_SYS_LONGHELP 176 177 #define CONFIG_FPGA_COUNT 1 178 #define CONFIG_FPGA_SPARTAN3 179 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 180 #define CONFIG_SYS_FPGA_WAIT 1000 181 182 /* End of user parameters to be customized */ 183 184 /* Defines memory range for test */ 185 186 #define CONFIG_SYS_MEMTEST_START 0x40020000 187 #define CONFIG_SYS_MEMTEST_END 0x41ffffff 188 189 /* 190 * Low Level Configuration Settings 191 * (address mappings, register initial values, etc.) 192 * You should know what you are doing if you make changes here. 193 */ 194 195 /* Base register address */ 196 197 #define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ 198 199 /* System Conf. Reg. & System Protection Reg. */ 200 201 #define CONFIG_SYS_SCR 0x0003; 202 #define CONFIG_SYS_SPR 0xffff; 203 204 /* 205 * Definitions for initial stack pointer and data area (in internal SRAM) 206 */ 207 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 208 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 209 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 210 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 211 GENERATED_GBL_DATA_SIZE) 212 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 213 214 /* 215 * Start addresses for the final memory configuration 216 * (Set up by the startup code) 217 * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 218 */ 219 #define CONFIG_SYS_SDRAM_BASE 0x40000000 220 221 /* 222 * Chipselect bank definitions 223 * 224 * CS0 - Flash 32MB (first 16MB) 225 * CS1 - Flash 32MB (second half) 226 * CS2 - FPGA 227 * CS3 - FPGA 228 * CS4 - unused 229 * CS5 - unused 230 */ 231 #define CONFIG_SYS_CS0_BASE 0 232 #define CONFIG_SYS_CS0_MASK 0x00ff0001 233 #define CONFIG_SYS_CS0_CTRL 0x00001fc0 234 235 #define CONFIG_SYS_CS1_BASE 0x01000000 236 #define CONFIG_SYS_CS1_MASK 0x00ff0001 237 #define CONFIG_SYS_CS1_CTRL 0x00001fc0 238 239 #define CONFIG_SYS_CS2_BASE 0x20000000 240 #define CONFIG_SYS_CS2_MASK 0x00ff0001 241 #define CONFIG_SYS_CS2_CTRL 0x0000fec0 242 243 #define CONFIG_SYS_CS3_BASE 0x21000000 244 #define CONFIG_SYS_CS3_MASK 0x00ff0001 245 #define CONFIG_SYS_CS3_CTRL 0x0000fec0 246 247 #define CONFIG_SYS_FLASH_BASE 0x00000000 248 249 #ifdef CONFIG_MONITOR_IS_IN_RAM 250 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 251 #else 252 /* This is mainly used during relocation in start.S */ 253 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 254 #endif 255 /* Reserve 256 kB for Monitor */ 256 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 257 258 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 259 /* Reserve 128 kB for malloc() */ 260 #define CONFIG_SYS_MALLOC_LEN (128 << 10) 261 262 /* 263 * For booting Linux, the board info and command line data 264 * have to be in the first 8 MB of memory, since this is 265 * the maximum mapped by the Linux kernel during initialization ?? 266 */ 267 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 268 (CONFIG_SYS_SDRAM_SIZE << 20)) 269 270 /* FLASH organization */ 271 #define CONFIG_SYS_MAX_FLASH_BANKS 1 272 #define CONFIG_SYS_MAX_FLASH_SECT 259 273 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 274 275 #define CONFIG_SYS_FLASH_CFI 1 276 #define CONFIG_FLASH_CFI_DRIVER 1 277 #define CONFIG_SYS_FLASH_SIZE 0x2000000 278 #define CONFIG_SYS_FLASH_PROTECTION 1 279 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 280 #define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 281 282 #define LDS_BOARD_TEXT \ 283 . = DEFINED(env_offset) ? env_offset : .; \ 284 env/embedded.o(.text*) 285 286 #if ENABLE_JFFS 287 /* JFFS Partition offset set */ 288 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 289 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 290 /* 512k reserved for u-boot */ 291 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 292 #endif 293 294 /* Cache Configuration */ 295 #define CONFIG_SYS_CACHELINE_SIZE 16 296 297 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 298 CONFIG_SYS_INIT_RAM_SIZE - 8) 299 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 300 CONFIG_SYS_INIT_RAM_SIZE - 4) 301 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 302 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 303 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 304 CF_ACR_EN | CF_ACR_SM_ALL) 305 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 306 CF_CACR_DCM_P) 307 308 #endif /* _CONFIG_ASTRO_MCF5373L_H */ 309