1 /* 2 * Copyright (C) 2013 Samsung Electronics 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Configuration settings for the SAMSUNG Arndale board. 7 */ 8 9 #ifndef __CONFIG_ARNDALE_H 10 #define __CONFIG_ARNDALE_H 11 12 /* High Level Configuration Options */ 13 #define CONFIG_SAMSUNG /* in a SAMSUNG core */ 14 #define CONFIG_S5P /* S5P Family */ 15 #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ 16 #define CONFIG_EXYNOS5250 17 18 #include <asm/arch/cpu.h> /* get chip and board defs */ 19 20 #define CONFIG_SYS_GENERIC_BOARD 21 #define CONFIG_ARCH_CPU_INIT 22 #define CONFIG_DISPLAY_CPUINFO 23 #define CONFIG_DISPLAY_BOARDINFO 24 25 #define CONFIG_OF_CONTROL 26 #define CONFIG_OF_SEPARATE 27 28 /* Allow tracing to be enabled */ 29 #define CONFIG_TRACE 30 #define CONFIG_CMD_TRACE 31 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) 32 #define CONFIG_TRACE_EARLY_SIZE (8 << 20) 33 #define CONFIG_TRACE_EARLY 34 #define CONFIG_TRACE_EARLY_ADDR 0x50000000 35 36 /* Keep L2 Cache Disabled */ 37 #define CONFIG_SYS_DCACHE_OFF 38 39 #define CONFIG_SYS_SDRAM_BASE 0x40000000 40 #define CONFIG_SYS_TEXT_BASE 0x43E00000 41 42 /* input clock of PLL: SMDK5250 has 24MHz input clock */ 43 #define CONFIG_SYS_CLK_FREQ 24000000 44 45 #define CONFIG_SETUP_MEMORY_TAGS 46 #define CONFIG_CMDLINE_TAG 47 #define CONFIG_INITRD_TAG 48 #define CONFIG_CMDLINE_EDITING 49 50 /* Power Down Modes */ 51 #define S5P_CHECK_SLEEP 0x00000BAD 52 #define S5P_CHECK_DIDLE 0xBAD00000 53 #define S5P_CHECK_LPA 0xABAD0000 54 55 /* Offset for inform registers */ 56 #define INFORM0_OFFSET 0x800 57 #define INFORM1_OFFSET 0x804 58 59 /* Size of malloc() pool */ 60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) 61 62 /* select serial console configuration */ 63 #define CONFIG_BAUDRATE 115200 64 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 65 #define CONFIG_SILENT_CONSOLE 66 67 /* Console configuration */ 68 #define CONFIG_CONSOLE_MUX 69 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 70 #define EXYNOS_DEVICE_SETTINGS \ 71 "stdin=serial\0" \ 72 "stdout=serial\0" \ 73 "stderr=serial\0" 74 75 #define CONFIG_EXTRA_ENV_SETTINGS \ 76 EXYNOS_DEVICE_SETTINGS 77 78 /* SD/MMC configuration */ 79 #define CONFIG_GENERIC_MMC 80 #define CONFIG_MMC 81 #define CONFIG_SDHCI 82 #define CONFIG_S5P_SDHCI 83 #define CONFIG_DWMMC 84 #define CONFIG_EXYNOS_DWMMC 85 #define CONFIG_SUPPORT_EMMC_BOOT 86 #define CONFIG_BOUNCE_BUFFER 87 88 89 #define CONFIG_BOARD_EARLY_INIT_F 90 #define CONFIG_SKIP_LOWLEVEL_INIT 91 92 /* PWM */ 93 #define CONFIG_PWM 94 95 /* allow to overwrite serial and ethaddr */ 96 #define CONFIG_ENV_OVERWRITE 97 98 /* Command definition*/ 99 #include <config_cmd_default.h> 100 101 #define CONFIG_CMD_PING 102 #define CONFIG_CMD_ELF 103 #define CONFIG_CMD_MMC 104 #define CONFIG_CMD_EXT2 105 #define CONFIG_CMD_FAT 106 #define CONFIG_CMD_NET 107 #define CONFIG_CMD_HASH 108 109 #define CONFIG_BOOTDELAY 3 110 #define CONFIG_ZERO_BOOTDELAY_CHECK 111 112 /* USB */ 113 #define CONFIG_CMD_USB 114 #define CONFIG_USB_EHCI 115 #define CONFIG_USB_EHCI_EXYNOS 116 #define CONFIG_USB_STORAGE 117 118 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 119 #define CONFIG_USB_HOST_ETHER 120 #define CONFIG_USB_ETHER_ASIX 121 122 /* MMC SPL */ 123 #define CONFIG_EXYNOS_SPL 124 #define CONFIG_SPL 125 #define COPY_BL2_FNPTR_ADDR 0x02020030 126 127 #define CONFIG_SPL_LIBCOMMON_SUPPORT 128 129 /* specific .lds file */ 130 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" 131 #define CONFIG_SPL_TEXT_BASE 0x02023400 132 #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) 133 134 #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" 135 136 /* Miscellaneous configurable options */ 137 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 138 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 139 #define CONFIG_SYS_PROMPT "ARNDALE # " 140 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 141 #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ 142 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 143 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" 144 /* Boot Argument Buffer Size */ 145 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 146 /* memtest works on */ 147 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 148 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) 149 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 150 151 #define CONFIG_RD_LVL 152 153 #define CONFIG_NR_DRAM_BANKS 8 154 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ 155 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 156 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 157 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 158 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 159 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 160 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 161 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 162 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 163 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 164 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 165 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 166 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 167 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 168 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 169 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 170 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 171 172 #define CONFIG_SYS_MONITOR_BASE 0x00000000 173 174 /* FLASH and environment organization */ 175 #define CONFIG_SYS_NO_FLASH 176 #undef CONFIG_CMD_IMLS 177 #define CONFIG_IDENT_STRING " for ARNDALE" 178 179 #define CONFIG_SYS_MMC_ENV_DEV 0 180 181 #define CONFIG_ENV_IS_IN_MMC 182 #define CONFIG_SECURE_BL1_ONLY 183 184 /* Secure FW size configuration */ 185 #ifdef CONFIG_SECURE_BL1_ONLY 186 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ 187 #else 188 #define CONFIG_SEC_FW_SIZE 0 189 #endif 190 191 /* Configuration of BL1, BL2, ENV Blocks on mmc */ 192 #define CONFIG_RES_BLOCK_SIZE (512) 193 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 194 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ 195 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 196 197 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) 198 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) 199 #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) 200 201 /* U-boot copy size from boot Media to DRAM.*/ 202 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) 203 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) 204 205 #define CONFIG_DOS_PARTITION 206 #define CONFIG_EFI_PARTITION 207 #define CONFIG_CMD_PART 208 #define CONFIG_PARTITION_UUIDS 209 210 211 #define CONFIG_IRAM_STACK 0x02050000 212 213 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK 214 215 /* I2C */ 216 #define CONFIG_SYS_I2C_INIT_BOARD 217 #define CONFIG_SYS_I2C 218 #define CONFIG_CMD_I2C 219 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ 220 #define CONFIG_SYS_I2C_S3C24X0 221 #define CONFIG_MAX_I2C_NUM 8 222 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 223 #define CONFIG_I2C_EDID 224 225 /* PMIC */ 226 #define CONFIG_PMIC 227 #define CONFIG_PMIC_I2C 228 #define CONFIG_PMIC_MAX77686 229 230 #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale 231 232 /* Ethernet Controllor Driver */ 233 #ifdef CONFIG_CMD_NET 234 #define CONFIG_SMC911X 235 #define CONFIG_SMC911X_BASE 0x5000000 236 #define CONFIG_SMC911X_16_BIT 237 #define CONFIG_ENV_SROM_BANK 1 238 #endif /*CONFIG_CMD_NET*/ 239 240 /* Enable PXE Support */ 241 #ifdef CONFIG_CMD_NET 242 #define CONFIG_CMD_PXE 243 #define CONFIG_MENU 244 #endif 245 246 /* Enable devicetree support */ 247 #define CONFIG_OF_LIBFDT 248 249 /* Enable Time Command */ 250 #define CONFIG_CMD_TIME 251 252 #endif /* __CONFIG_H */ 253