1 /* 2 * 3 * Configuration settings for the Armadeus Project motherboard APF27 4 * 5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_ENV_VERSION 10 14 #define CONFIG_BOARD_NAME apf27 15 16 /* 17 * SoC configurations 18 */ 19 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ 20 #define CONFIG_MACH_TYPE 1698 /* APF27 */ 21 22 /* 23 * Enable the call to miscellaneous platform dependent initialization. 24 */ 25 #define CONFIG_SYS_NO_FLASH 26 27 /* 28 * SPL 29 */ 30 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 31 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 32 #define CONFIG_SPL_MAX_SIZE 2048 33 #define CONFIG_SPL_TEXT_BASE 0xA0000000 34 35 /* NAND boot config */ 36 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 37 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 38 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 39 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 40 41 /* 42 * BOOTP options 43 */ 44 #define CONFIG_BOOTP_SUBNETMASK 45 #define CONFIG_BOOTP_GATEWAY 46 #define CONFIG_BOOTP_HOSTNAME 47 #define CONFIG_BOOTP_BOOTPATH 48 #define CONFIG_BOOTP_BOOTFILESIZE 49 #define CONFIG_BOOTP_DNS 50 #define CONFIG_BOOTP_DNS2 51 52 #define CONFIG_HOSTNAME CONFIG_BOARD_NAME 53 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" 54 55 /* 56 * U-Boot Commands 57 */ 58 #define CONFIG_CMD_BSP /* Board Specific functions */ 59 #define CONFIG_CMD_DATE 60 #define CONFIG_CMD_EEPROM 61 #define CONFIG_CMD_IMX_FUSE /* imx iim fuse */ 62 #define CONFIG_CMD_MTDPARTS /* MTD partition support */ 63 #define CONFIG_CMD_NAND /* NAND support */ 64 #define CONFIG_CMD_NAND_LOCK_UNLOCK 65 #define CONFIG_CMD_NAND_TRIMFFS 66 #define CONFIG_CMD_UBIFS 67 68 /* 69 * Memory configurations 70 */ 71 #define CONFIG_NR_DRAM_POPULATED 1 72 #define CONFIG_NR_DRAM_BANKS 2 73 74 #define ACFG_SDRAM_MBYTE_SYZE 64 75 76 #define PHYS_SDRAM_1 0xA0000000 77 #define PHYS_SDRAM_2 0xB0000000 78 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 79 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) 80 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ 81 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ 82 83 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ 84 + PHYS_SDRAM_1_SIZE - 0x0100000) 85 86 #define CONFIG_SYS_TEXT_BASE 0xA0000800 87 88 /* 89 * FLASH organization 90 */ 91 #define ACFG_MONITOR_OFFSET 0x00000000 92 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ 93 #define CONFIG_ENV_IS_IN_NAND 94 #define CONFIG_ENV_OVERWRITE 95 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ 96 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ 97 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ 98 #define CONFIG_ENV_OFFSET_REDUND \ 99 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ 100 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ 101 #define CONFIG_FIRMWARE_OFFSET 0x00200000 102 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ 103 #define CONFIG_KERNEL_OFFSET 0x00300000 104 #define CONFIG_ROOTFS_OFFSET 0x00800000 105 106 #define CONFIG_MTDMAP "mxc_nand.0" 107 #define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP 108 #define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \ 109 ":1M(u-boot)ro," \ 110 "512K(env)," \ 111 "512K(env2)," \ 112 "512K(firmware)," \ 113 "512K(dtb)," \ 114 "5M(kernel)," \ 115 "-(rootfs)" 116 117 /* 118 * U-Boot general configurations 119 */ 120 #define CONFIG_SYS_LONGHELP 121 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ 122 #define CONFIG_SYS_PBSIZE \ 123 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 124 /* Print buffer size */ 125 #define CONFIG_SYS_MAXARGS 16 /* max command args */ 126 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 127 /* Boot argument buffer size */ 128 #define CONFIG_AUTO_COMPLETE 129 #define CONFIG_CMDLINE_EDITING 130 #define CONFIG_ENV_VARS_UBOOT_CONFIG 131 #define CONFIG_PREBOOT "run check_flash check_env;" 132 133 /* 134 * Boot Linux 135 */ 136 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 137 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 138 #define CONFIG_INITRD_TAG /* send initrd params */ 139 140 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" 141 #define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \ 142 __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \ 143 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " 144 145 #define ACFG_CONSOLE_DEV ttySMX0 146 #define CONFIG_BOOTCOMMAND "run ubifsboot" 147 #define CONFIG_SYS_AUTOLOAD "no" 148 /* 149 * Default load address for user programs and kernel 150 */ 151 #define CONFIG_LOADADDR 0xA0000000 152 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 153 154 /* 155 * Extra Environments 156 */ 157 #define CONFIG_EXTRA_ENV_SETTINGS \ 158 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ 159 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ 160 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 161 "partition=nand0,6\0" \ 162 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ 163 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ 164 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ 165 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ 166 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ 167 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ 168 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ 169 "kernel_addr_r=A0000000\0" \ 170 "check_env=if test -n ${flash_env_version}; " \ 171 "then env default env_version; " \ 172 "else env set flash_env_version ${env_version}; env save; "\ 173 "fi; " \ 174 "if itest ${flash_env_version} < ${env_version}; then " \ 175 "echo \"*** Warning - Environment version" \ 176 " change suggests: run flash_reset_env; reset\"; "\ 177 "env default flash_reset_env; "\ 178 "fi; \0" \ 179 "check_flash=nand lock; nand unlock ${env_addr}; \0" \ 180 "flash_reset_env=env default -f -a; saveenv; run update_env;" \ 181 "echo Flash environment variables erased!\0" \ 182 "download_uboot=tftpboot ${loadaddr} ${board_name}" \ 183 "-u-boot-with-spl.bin\0" \ 184 "flash_uboot=nand unlock ${u-boot_addr} ;" \ 185 "nand erase.part u-boot;" \ 186 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ 187 "then nand lock; nand unlock ${env_addr};" \ 188 "echo Flashing of uboot succeed;" \ 189 "else echo Flashing of uboot failed;" \ 190 "fi; \0" \ 191 "update_uboot=run download_uboot flash_uboot\0" \ 192 "download_env=tftpboot ${loadaddr} ${board_name}" \ 193 "-u-boot-env.txt\0" \ 194 "flash_env=env import -t ${loadaddr}; env save; \0" \ 195 "update_env=run download_env flash_env\0" \ 196 "update_all=run update_env update_uboot\0" \ 197 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ 198 199 /* 200 * Serial Driver 201 */ 202 #define CONFIG_MXC_UART 203 #define CONFIG_CONS_INDEX 1 204 #define CONFIG_BAUDRATE 115200 205 #define CONFIG_MXC_UART_BASE UART1_BASE 206 207 /* 208 * GPIO 209 */ 210 #define CONFIG_MXC_GPIO 211 212 /* 213 * NOR 214 */ 215 216 /* 217 * NAND 218 */ 219 #define CONFIG_NAND_MXC 220 221 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 222 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE 223 #define CONFIG_SYS_MAX_NAND_DEVICE 1 224 225 #define CONFIG_MXC_NAND_HWECC 226 #define CONFIG_SYS_NAND_LARGEPAGE 227 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 228 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 229 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 230 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ 231 CONFIG_SYS_NAND_PAGE_SIZE 232 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 233 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 234 #define NAND_MAX_CHIPS 1 235 236 #define CONFIG_FLASH_SHOW_PROGRESS 45 237 #define CONFIG_SYS_NAND_QUIET 1 238 239 /* 240 * Partitions & Filsystems 241 */ 242 #define CONFIG_MTD_DEVICE 243 #define CONFIG_MTD_PARTITIONS 244 #define CONFIG_SUPPORT_VFAT 245 246 /* 247 * UBIFS 248 */ 249 #define CONFIG_RBTREE 250 #define CONFIG_LZO 251 252 /* 253 * Ethernet (on SOC imx FEC) 254 */ 255 #define CONFIG_FEC_MXC 256 #define CONFIG_FEC_MXC_PHYADDR 0x1f 257 #define CONFIG_MII /* MII PHY management */ 258 259 /* 260 * FPGA 261 */ 262 #ifndef CONFIG_SPL_BUILD 263 #define CONFIG_FPGA 264 #endif 265 #define CONFIG_FPGA_COUNT 1 266 #define CONFIG_FPGA_XILINX 267 #define CONFIG_FPGA_SPARTAN3 268 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ 269 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 270 #define CONFIG_SYS_FPGA_CHECK_CTRLC 271 #define CONFIG_SYS_FPGA_CHECK_ERROR 272 273 /* 274 * Fuses - IIM 275 */ 276 #ifdef CONFIG_CMD_IMX_FUSE 277 #define IIM_MAC_BANK 0 278 #define IIM_MAC_ROW 5 279 #define IIM0_SCC_KEY 11 280 #define IIM1_SUID 1 281 #endif 282 283 /* 284 * I2C 285 */ 286 287 #ifdef CONFIG_CMD_I2C 288 #define CONFIG_SYS_I2C 289 #define CONFIG_SYS_I2C_MXC 290 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 291 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 292 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ 293 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F 294 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ 295 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F 296 #define CONFIG_SYS_I2C_NOPROBES { } 297 298 #ifdef CONFIG_CMD_EEPROM 299 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ 300 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 301 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 302 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ 303 #endif /* CONFIG_CMD_EEPROM */ 304 #endif /* CONFIG_CMD_I2C */ 305 306 /* 307 * SD/MMC 308 */ 309 #ifdef CONFIG_CMD_MMC 310 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 311 #endif 312 313 /* 314 * RTC 315 */ 316 #ifdef CONFIG_CMD_DATE 317 #define CONFIG_RTC_DS1374 318 #define CONFIG_SYS_RTC_BUS_NUM 0 319 #endif /* CONFIG_CMD_DATE */ 320 321 /* 322 * PLL 323 * 324 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 325 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| 326 */ 327 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ 328 329 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 330 /* micron 64MB */ 331 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 332 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ 333 #endif 334 335 #if (ACFG_SDRAM_MBYTE_SYZE == 128) 336 /* micron 128MB */ 337 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 338 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ 339 #endif 340 341 #if (ACFG_SDRAM_MBYTE_SYZE == 256) 342 /* micron 256MB */ 343 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ 344 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ 345 #endif 346 347 #endif /* __CONFIG_H */ 348