1 /* 2 * 3 * Configuration settings for the Armadeus Project motherboard APF27 4 * 5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_VERSION_VARIABLE 14 #define CONFIG_ENV_VERSION 10 15 #define CONFIG_IDENT_STRING " apf27 patch 3.10" 16 #define CONFIG_BOARD_NAME apf27 17 18 /* 19 * SoC configurations 20 */ 21 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ 22 #define CONFIG_MACH_TYPE 1698 /* APF27 */ 23 24 /* 25 * Enable the call to miscellaneous platform dependent initialization. 26 */ 27 #define CONFIG_SYS_NO_FLASH 28 29 /* 30 * Board display option 31 */ 32 #define CONFIG_DISPLAY_BOARDINFO 33 #define CONFIG_DISPLAY_CPUINFO 34 35 /* 36 * SPL 37 */ 38 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 39 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 40 #define CONFIG_SPL_MAX_SIZE 2048 41 #define CONFIG_SPL_TEXT_BASE 0xA0000000 42 #define CONFIG_SPL_SERIAL_SUPPORT 43 44 /* NAND boot config */ 45 #define CONFIG_SPL_NAND_SUPPORT 46 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 48 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 50 51 /* 52 * BOOTP options 53 */ 54 #define CONFIG_BOOTP_SUBNETMASK 55 #define CONFIG_BOOTP_GATEWAY 56 #define CONFIG_BOOTP_HOSTNAME 57 #define CONFIG_BOOTP_BOOTPATH 58 #define CONFIG_BOOTP_BOOTFILESIZE 59 #define CONFIG_BOOTP_DNS 60 #define CONFIG_BOOTP_DNS2 61 62 #define CONFIG_HOSTNAME CONFIG_BOARD_NAME 63 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" 64 65 /* 66 * U-Boot Commands 67 */ 68 #define CONFIG_CMD_BSP /* Board Specific functions */ 69 #define CONFIG_CMD_DATE 70 #define CONFIG_CMD_EEPROM 71 #define CONFIG_CMD_IMX_FUSE /* imx iim fuse */ 72 #define CONFIG_CMD_MTDPARTS /* MTD partition support */ 73 #define CONFIG_CMD_NAND /* NAND support */ 74 #define CONFIG_CMD_NAND_LOCK_UNLOCK 75 #define CONFIG_CMD_NAND_TRIMFFS 76 #define CONFIG_CMD_UBI 77 #define CONFIG_CMD_UBIFS 78 79 /* 80 * Memory configurations 81 */ 82 #define CONFIG_NR_DRAM_POPULATED 1 83 #define CONFIG_NR_DRAM_BANKS 2 84 85 #define ACFG_SDRAM_MBYTE_SYZE 64 86 87 #define PHYS_SDRAM_1 0xA0000000 88 #define PHYS_SDRAM_2 0xB0000000 89 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 90 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) 91 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ 92 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ 93 94 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ 95 + PHYS_SDRAM_1_SIZE - 0x0100000) 96 97 #define CONFIG_SYS_TEXT_BASE 0xA0000800 98 99 /* 100 * FLASH organization 101 */ 102 #define ACFG_MONITOR_OFFSET 0x00000000 103 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ 104 #define CONFIG_ENV_IS_IN_NAND 105 #define CONFIG_ENV_OVERWRITE 106 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ 107 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ 108 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ 109 #define CONFIG_ENV_OFFSET_REDUND \ 110 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ 111 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ 112 #define CONFIG_FIRMWARE_OFFSET 0x00200000 113 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ 114 #define CONFIG_KERNEL_OFFSET 0x00300000 115 #define CONFIG_ROOTFS_OFFSET 0x00800000 116 117 #define CONFIG_MTDMAP "mxc_nand.0" 118 #define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP 119 #define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \ 120 ":1M(u-boot)ro," \ 121 "512K(env)," \ 122 "512K(env2)," \ 123 "512K(firmware)," \ 124 "512K(dtb)," \ 125 "5M(kernel)," \ 126 "-(rootfs)" 127 128 /* 129 * U-Boot general configurations 130 */ 131 #define CONFIG_SYS_LONGHELP 132 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ 133 #define CONFIG_SYS_PBSIZE \ 134 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 135 /* Print buffer size */ 136 #define CONFIG_SYS_MAXARGS 16 /* max command args */ 137 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 138 /* Boot argument buffer size */ 139 #define CONFIG_AUTO_COMPLETE 140 #define CONFIG_CMDLINE_EDITING 141 #define CONFIG_ENV_VARS_UBOOT_CONFIG 142 #define CONFIG_PREBOOT "run check_flash check_env;" 143 144 /* 145 * Boot Linux 146 */ 147 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 148 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 149 #define CONFIG_INITRD_TAG /* send initrd params */ 150 151 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" 152 #define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \ 153 __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \ 154 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " 155 156 #define ACFG_CONSOLE_DEV ttySMX0 157 #define CONFIG_BOOTCOMMAND "run ubifsboot" 158 #define CONFIG_SYS_AUTOLOAD "no" 159 /* 160 * Default load address for user programs and kernel 161 */ 162 #define CONFIG_LOADADDR 0xA0000000 163 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 164 165 /* 166 * Extra Environments 167 */ 168 #define CONFIG_EXTRA_ENV_SETTINGS \ 169 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ 170 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ 171 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 172 "partition=nand0,6\0" \ 173 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ 174 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ 175 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ 176 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ 177 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ 178 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ 179 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ 180 "kernel_addr_r=A0000000\0" \ 181 "check_env=if test -n ${flash_env_version}; " \ 182 "then env default env_version; " \ 183 "else env set flash_env_version ${env_version}; env save; "\ 184 "fi; " \ 185 "if itest ${flash_env_version} < ${env_version}; then " \ 186 "echo \"*** Warning - Environment version" \ 187 " change suggests: run flash_reset_env; reset\"; "\ 188 "env default flash_reset_env; "\ 189 "fi; \0" \ 190 "check_flash=nand lock; nand unlock ${env_addr}; \0" \ 191 "flash_reset_env=env default -f -a; saveenv; run update_env;" \ 192 "echo Flash environment variables erased!\0" \ 193 "download_uboot=tftpboot ${loadaddr} ${board_name}" \ 194 "-u-boot-with-spl.bin\0" \ 195 "flash_uboot=nand unlock ${u-boot_addr} ;" \ 196 "nand erase.part u-boot;" \ 197 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ 198 "then nand lock; nand unlock ${env_addr};" \ 199 "echo Flashing of uboot succeed;" \ 200 "else echo Flashing of uboot failed;" \ 201 "fi; \0" \ 202 "update_uboot=run download_uboot flash_uboot\0" \ 203 "download_env=tftpboot ${loadaddr} ${board_name}" \ 204 "-u-boot-env.txt\0" \ 205 "flash_env=env import -t ${loadaddr}; env save; \0" \ 206 "update_env=run download_env flash_env\0" \ 207 "update_all=run update_env update_uboot\0" \ 208 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ 209 210 /* 211 * Serial Driver 212 */ 213 #define CONFIG_MXC_UART 214 #define CONFIG_CONS_INDEX 1 215 #define CONFIG_BAUDRATE 115200 216 #define CONFIG_MXC_UART_BASE UART1_BASE 217 218 /* 219 * GPIO 220 */ 221 #define CONFIG_MXC_GPIO 222 223 /* 224 * NOR 225 */ 226 227 /* 228 * NAND 229 */ 230 #define CONFIG_NAND_MXC 231 232 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 233 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE 234 #define CONFIG_SYS_MAX_NAND_DEVICE 1 235 236 #define CONFIG_MXC_NAND_HWECC 237 #define CONFIG_SYS_NAND_LARGEPAGE 238 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 239 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 240 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 241 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ 242 CONFIG_SYS_NAND_PAGE_SIZE 243 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 244 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 245 #define NAND_MAX_CHIPS 1 246 247 #define CONFIG_FLASH_SHOW_PROGRESS 45 248 #define CONFIG_SYS_NAND_QUIET 1 249 250 /* 251 * Partitions & Filsystems 252 */ 253 #define CONFIG_MTD_DEVICE 254 #define CONFIG_MTD_PARTITIONS 255 #define CONFIG_DOS_PARTITION 256 #define CONFIG_SUPPORT_VFAT 257 258 /* 259 * UBIFS 260 */ 261 #define CONFIG_RBTREE 262 #define CONFIG_LZO 263 264 /* 265 * Ethernet (on SOC imx FEC) 266 */ 267 #define CONFIG_FEC_MXC 268 #define CONFIG_FEC_MXC_PHYADDR 0x1f 269 #define CONFIG_MII /* MII PHY management */ 270 271 /* 272 * FPGA 273 */ 274 #ifndef CONFIG_SPL_BUILD 275 #define CONFIG_FPGA 276 #endif 277 #define CONFIG_FPGA_COUNT 1 278 #define CONFIG_FPGA_XILINX 279 #define CONFIG_FPGA_SPARTAN3 280 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ 281 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 282 #define CONFIG_SYS_FPGA_CHECK_CTRLC 283 #define CONFIG_SYS_FPGA_CHECK_ERROR 284 285 /* 286 * Fuses - IIM 287 */ 288 #ifdef CONFIG_CMD_IMX_FUSE 289 #define IIM_MAC_BANK 0 290 #define IIM_MAC_ROW 5 291 #define IIM0_SCC_KEY 11 292 #define IIM1_SUID 1 293 #endif 294 295 /* 296 * I2C 297 */ 298 299 #ifdef CONFIG_CMD_I2C 300 #define CONFIG_SYS_I2C 301 #define CONFIG_SYS_I2C_MXC 302 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 303 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 304 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ 305 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F 306 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ 307 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F 308 #define CONFIG_SYS_I2C_NOPROBES { } 309 310 #ifdef CONFIG_CMD_EEPROM 311 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ 312 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 313 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ 315 #endif /* CONFIG_CMD_EEPROM */ 316 #endif /* CONFIG_CMD_I2C */ 317 318 /* 319 * SD/MMC 320 */ 321 #ifdef CONFIG_CMD_MMC 322 #define CONFIG_MMC 323 #define CONFIG_GENERIC_MMC 324 #define CONFIG_MXC_MMC 325 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 326 #endif 327 328 /* 329 * RTC 330 */ 331 #ifdef CONFIG_CMD_DATE 332 #define CONFIG_RTC_DS1374 333 #define CONFIG_SYS_RTC_BUS_NUM 0 334 #endif /* CONFIG_CMD_DATE */ 335 336 /* 337 * PLL 338 * 339 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 340 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| 341 */ 342 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ 343 344 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 345 /* micron 64MB */ 346 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 347 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ 348 #endif 349 350 #if (ACFG_SDRAM_MBYTE_SYZE == 128) 351 /* micron 128MB */ 352 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 353 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ 354 #endif 355 356 #if (ACFG_SDRAM_MBYTE_SYZE == 256) 357 /* micron 256MB */ 358 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ 359 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ 360 #endif 361 362 #endif /* __CONFIG_H */ 363