1 /* 2 * 3 * Configuration settings for the Armadeus Project motherboard APF27 4 * 5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_ENV_VERSION 10 14 #define CONFIG_BOARD_NAME apf27 15 16 /* 17 * SoC configurations 18 */ 19 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ 20 #define CONFIG_MACH_TYPE 1698 /* APF27 */ 21 22 /* 23 * Enable the call to miscellaneous platform dependent initialization. 24 */ 25 26 /* 27 * SPL 28 */ 29 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 30 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 31 #define CONFIG_SPL_MAX_SIZE 2048 32 #define CONFIG_SPL_TEXT_BASE 0xA0000000 33 34 /* NAND boot config */ 35 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 36 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 37 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 38 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 39 40 /* 41 * BOOTP options 42 */ 43 #define CONFIG_BOOTP_SUBNETMASK 44 #define CONFIG_BOOTP_GATEWAY 45 #define CONFIG_BOOTP_HOSTNAME 46 #define CONFIG_BOOTP_BOOTPATH 47 #define CONFIG_BOOTP_BOOTFILESIZE 48 #define CONFIG_BOOTP_DNS 49 #define CONFIG_BOOTP_DNS2 50 51 #define CONFIG_HOSTNAME CONFIG_BOARD_NAME 52 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" 53 54 /* 55 * U-Boot Commands 56 */ 57 #define CONFIG_CMD_BSP /* Board Specific functions */ 58 #define CONFIG_CMD_DATE 59 #define CONFIG_CMD_EEPROM 60 #define CONFIG_CMD_IMX_FUSE /* imx iim fuse */ 61 #define CONFIG_CMD_MTDPARTS /* MTD partition support */ 62 #define CONFIG_CMD_NAND /* NAND support */ 63 #define CONFIG_CMD_NAND_LOCK_UNLOCK 64 #define CONFIG_CMD_NAND_TRIMFFS 65 #define CONFIG_CMD_UBIFS 66 67 /* 68 * Memory configurations 69 */ 70 #define CONFIG_NR_DRAM_POPULATED 1 71 #define CONFIG_NR_DRAM_BANKS 2 72 73 #define ACFG_SDRAM_MBYTE_SYZE 64 74 75 #define PHYS_SDRAM_1 0xA0000000 76 #define PHYS_SDRAM_2 0xB0000000 77 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 78 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) 79 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ 80 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ 81 82 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ 83 + PHYS_SDRAM_1_SIZE - 0x0100000) 84 85 #define CONFIG_SYS_TEXT_BASE 0xA0000800 86 87 /* 88 * FLASH organization 89 */ 90 #define ACFG_MONITOR_OFFSET 0x00000000 91 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ 92 #define CONFIG_ENV_IS_IN_NAND 93 #define CONFIG_ENV_OVERWRITE 94 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ 95 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ 96 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ 97 #define CONFIG_ENV_OFFSET_REDUND \ 98 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ 99 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ 100 #define CONFIG_FIRMWARE_OFFSET 0x00200000 101 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ 102 #define CONFIG_KERNEL_OFFSET 0x00300000 103 #define CONFIG_ROOTFS_OFFSET 0x00800000 104 105 #define CONFIG_MTDMAP "mxc_nand.0" 106 #define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP 107 #define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \ 108 ":1M(u-boot)ro," \ 109 "512K(env)," \ 110 "512K(env2)," \ 111 "512K(firmware)," \ 112 "512K(dtb)," \ 113 "5M(kernel)," \ 114 "-(rootfs)" 115 116 /* 117 * U-Boot general configurations 118 */ 119 #define CONFIG_SYS_LONGHELP 120 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ 121 #define CONFIG_SYS_PBSIZE \ 122 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 123 /* Print buffer size */ 124 #define CONFIG_SYS_MAXARGS 16 /* max command args */ 125 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 126 /* Boot argument buffer size */ 127 #define CONFIG_AUTO_COMPLETE 128 #define CONFIG_CMDLINE_EDITING 129 #define CONFIG_ENV_VARS_UBOOT_CONFIG 130 #define CONFIG_PREBOOT "run check_flash check_env;" 131 132 /* 133 * Boot Linux 134 */ 135 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 136 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 137 #define CONFIG_INITRD_TAG /* send initrd params */ 138 139 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" 140 #define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \ 141 __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \ 142 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " 143 144 #define ACFG_CONSOLE_DEV ttySMX0 145 #define CONFIG_BOOTCOMMAND "run ubifsboot" 146 #define CONFIG_SYS_AUTOLOAD "no" 147 /* 148 * Default load address for user programs and kernel 149 */ 150 #define CONFIG_LOADADDR 0xA0000000 151 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 152 153 /* 154 * Extra Environments 155 */ 156 #define CONFIG_EXTRA_ENV_SETTINGS \ 157 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ 158 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ 159 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 160 "partition=nand0,6\0" \ 161 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ 162 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ 163 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ 164 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ 165 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ 166 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ 167 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ 168 "kernel_addr_r=A0000000\0" \ 169 "check_env=if test -n ${flash_env_version}; " \ 170 "then env default env_version; " \ 171 "else env set flash_env_version ${env_version}; env save; "\ 172 "fi; " \ 173 "if itest ${flash_env_version} < ${env_version}; then " \ 174 "echo \"*** Warning - Environment version" \ 175 " change suggests: run flash_reset_env; reset\"; "\ 176 "env default flash_reset_env; "\ 177 "fi; \0" \ 178 "check_flash=nand lock; nand unlock ${env_addr}; \0" \ 179 "flash_reset_env=env default -f -a; saveenv; run update_env;" \ 180 "echo Flash environment variables erased!\0" \ 181 "download_uboot=tftpboot ${loadaddr} ${board_name}" \ 182 "-u-boot-with-spl.bin\0" \ 183 "flash_uboot=nand unlock ${u-boot_addr} ;" \ 184 "nand erase.part u-boot;" \ 185 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ 186 "then nand lock; nand unlock ${env_addr};" \ 187 "echo Flashing of uboot succeed;" \ 188 "else echo Flashing of uboot failed;" \ 189 "fi; \0" \ 190 "update_uboot=run download_uboot flash_uboot\0" \ 191 "download_env=tftpboot ${loadaddr} ${board_name}" \ 192 "-u-boot-env.txt\0" \ 193 "flash_env=env import -t ${loadaddr}; env save; \0" \ 194 "update_env=run download_env flash_env\0" \ 195 "update_all=run update_env update_uboot\0" \ 196 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ 197 198 /* 199 * Serial Driver 200 */ 201 #define CONFIG_MXC_UART 202 #define CONFIG_CONS_INDEX 1 203 #define CONFIG_BAUDRATE 115200 204 #define CONFIG_MXC_UART_BASE UART1_BASE 205 206 /* 207 * GPIO 208 */ 209 #define CONFIG_MXC_GPIO 210 211 /* 212 * NOR 213 */ 214 215 /* 216 * NAND 217 */ 218 #define CONFIG_NAND_MXC 219 220 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 221 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE 222 #define CONFIG_SYS_MAX_NAND_DEVICE 1 223 224 #define CONFIG_MXC_NAND_HWECC 225 #define CONFIG_SYS_NAND_LARGEPAGE 226 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 227 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 228 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 229 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ 230 CONFIG_SYS_NAND_PAGE_SIZE 231 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 232 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 233 #define NAND_MAX_CHIPS 1 234 235 #define CONFIG_FLASH_SHOW_PROGRESS 45 236 #define CONFIG_SYS_NAND_QUIET 1 237 238 /* 239 * Partitions & Filsystems 240 */ 241 #define CONFIG_MTD_DEVICE 242 #define CONFIG_MTD_PARTITIONS 243 #define CONFIG_SUPPORT_VFAT 244 245 /* 246 * UBIFS 247 */ 248 #define CONFIG_RBTREE 249 #define CONFIG_LZO 250 251 /* 252 * Ethernet (on SOC imx FEC) 253 */ 254 #define CONFIG_FEC_MXC 255 #define CONFIG_FEC_MXC_PHYADDR 0x1f 256 #define CONFIG_MII /* MII PHY management */ 257 258 /* 259 * FPGA 260 */ 261 #ifndef CONFIG_SPL_BUILD 262 #define CONFIG_FPGA 263 #endif 264 #define CONFIG_FPGA_COUNT 1 265 #define CONFIG_FPGA_XILINX 266 #define CONFIG_FPGA_SPARTAN3 267 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ 268 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 269 #define CONFIG_SYS_FPGA_CHECK_CTRLC 270 #define CONFIG_SYS_FPGA_CHECK_ERROR 271 272 /* 273 * Fuses - IIM 274 */ 275 #ifdef CONFIG_CMD_IMX_FUSE 276 #define IIM_MAC_BANK 0 277 #define IIM_MAC_ROW 5 278 #define IIM0_SCC_KEY 11 279 #define IIM1_SUID 1 280 #endif 281 282 /* 283 * I2C 284 */ 285 286 #ifdef CONFIG_CMD_I2C 287 #define CONFIG_SYS_I2C 288 #define CONFIG_SYS_I2C_MXC 289 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 290 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 291 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ 292 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F 293 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ 294 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F 295 #define CONFIG_SYS_I2C_NOPROBES { } 296 297 #ifdef CONFIG_CMD_EEPROM 298 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ 299 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 300 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 301 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ 302 #endif /* CONFIG_CMD_EEPROM */ 303 #endif /* CONFIG_CMD_I2C */ 304 305 /* 306 * SD/MMC 307 */ 308 #ifdef CONFIG_CMD_MMC 309 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 310 #endif 311 312 /* 313 * RTC 314 */ 315 #ifdef CONFIG_CMD_DATE 316 #define CONFIG_RTC_DS1374 317 #define CONFIG_SYS_RTC_BUS_NUM 0 318 #endif /* CONFIG_CMD_DATE */ 319 320 /* 321 * PLL 322 * 323 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 324 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| 325 */ 326 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ 327 328 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 329 /* micron 64MB */ 330 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 331 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ 332 #endif 333 334 #if (ACFG_SDRAM_MBYTE_SYZE == 128) 335 /* micron 128MB */ 336 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 337 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ 338 #endif 339 340 #if (ACFG_SDRAM_MBYTE_SYZE == 256) 341 /* micron 256MB */ 342 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ 343 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ 344 #endif 345 346 #endif /* __CONFIG_H */ 347