1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * 4 * Configuration settings for the Armadeus Project motherboard APF27 5 * 6 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_ENV_VERSION 10 13 #define CONFIG_BOARD_NAME apf27 14 15 /* 16 * SoC configurations 17 */ 18 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ 19 #define CONFIG_MACH_TYPE 1698 /* APF27 */ 20 21 /* 22 * Enable the call to miscellaneous platform dependent initialization. 23 */ 24 25 /* 26 * SPL 27 */ 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_SPL_MAX_SIZE 2048 30 #define CONFIG_SPL_TEXT_BASE 0xA0000000 31 32 /* NAND boot config */ 33 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 34 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 35 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 36 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 37 38 /* 39 * BOOTP options 40 */ 41 #define CONFIG_BOOTP_BOOTFILESIZE 42 #define CONFIG_BOOTP_DNS2 43 44 #define CONFIG_HOSTNAME "apf27" 45 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" 46 47 /* 48 * Memory configurations 49 */ 50 #define CONFIG_NR_DRAM_POPULATED 1 51 #define CONFIG_NR_DRAM_BANKS 2 52 53 #define ACFG_SDRAM_MBYTE_SYZE 64 54 55 #define PHYS_SDRAM_1 0xA0000000 56 #define PHYS_SDRAM_2 0xB0000000 57 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 58 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) 59 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ 60 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ 61 62 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ 63 + PHYS_SDRAM_1_SIZE - 0x0100000) 64 65 /* 66 * FLASH organization 67 */ 68 #define ACFG_MONITOR_OFFSET 0x00000000 69 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ 70 #define CONFIG_ENV_OVERWRITE 71 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ 72 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ 73 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ 74 #define CONFIG_ENV_OFFSET_REDUND \ 75 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ 76 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ 77 #define CONFIG_FIRMWARE_OFFSET 0x00200000 78 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ 79 #define CONFIG_KERNEL_OFFSET 0x00300000 80 #define CONFIG_ROOTFS_OFFSET 0x00800000 81 82 /* 83 * U-Boot general configurations 84 */ 85 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ 86 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 87 /* Boot argument buffer size */ 88 #define CONFIG_PREBOOT "run check_flash check_env;" 89 90 /* 91 * Boot Linux 92 */ 93 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 94 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 95 #define CONFIG_INITRD_TAG /* send initrd params */ 96 97 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" 98 99 #define ACFG_CONSOLE_DEV ttySMX0 100 #define CONFIG_BOOTCOMMAND "run ubifsboot" 101 #define CONFIG_SYS_AUTOLOAD "no" 102 /* 103 * Default load address for user programs and kernel 104 */ 105 #define CONFIG_LOADADDR 0xA0000000 106 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 107 108 /* 109 * Extra Environments 110 */ 111 #define CONFIG_EXTRA_ENV_SETTINGS \ 112 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ 113 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ 114 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 115 "partition=nand0,6\0" \ 116 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ 117 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ 118 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ 119 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ 120 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ 121 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ 122 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ 123 "kernel_addr_r=A0000000\0" \ 124 "check_env=if test -n ${flash_env_version}; " \ 125 "then env default env_version; " \ 126 "else env set flash_env_version ${env_version}; env save; "\ 127 "fi; " \ 128 "if itest ${flash_env_version} < ${env_version}; then " \ 129 "echo \"*** Warning - Environment version" \ 130 " change suggests: run flash_reset_env; reset\"; "\ 131 "env default flash_reset_env; "\ 132 "fi; \0" \ 133 "check_flash=nand lock; nand unlock ${env_addr}; \0" \ 134 "flash_reset_env=env default -f -a; saveenv; run update_env;" \ 135 "echo Flash environment variables erased!\0" \ 136 "download_uboot=tftpboot ${loadaddr} ${board_name}" \ 137 "-u-boot-with-spl.bin\0" \ 138 "flash_uboot=nand unlock ${u-boot_addr} ;" \ 139 "nand erase.part u-boot;" \ 140 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ 141 "then nand lock; nand unlock ${env_addr};" \ 142 "echo Flashing of uboot succeed;" \ 143 "else echo Flashing of uboot failed;" \ 144 "fi; \0" \ 145 "update_uboot=run download_uboot flash_uboot\0" \ 146 "download_env=tftpboot ${loadaddr} ${board_name}" \ 147 "-u-boot-env.txt\0" \ 148 "flash_env=env import -t ${loadaddr}; env save; \0" \ 149 "update_env=run download_env flash_env\0" \ 150 "update_all=run update_env update_uboot\0" \ 151 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ 152 153 /* 154 * Serial Driver 155 */ 156 #define CONFIG_MXC_UART 157 #define CONFIG_MXC_UART_BASE UART1_BASE 158 159 /* 160 * NOR 161 */ 162 163 /* 164 * NAND 165 */ 166 167 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 168 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE 169 #define CONFIG_SYS_MAX_NAND_DEVICE 1 170 171 #define CONFIG_MXC_NAND_HWECC 172 #define CONFIG_SYS_NAND_LARGEPAGE 173 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 174 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 175 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ 176 CONFIG_SYS_NAND_PAGE_SIZE 177 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 178 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 179 #define NAND_MAX_CHIPS 1 180 181 #define CONFIG_FLASH_SHOW_PROGRESS 45 182 #define CONFIG_SYS_NAND_QUIET 1 183 184 /* 185 * Partitions & Filsystems 186 */ 187 188 /* 189 * Ethernet (on SOC imx FEC) 190 */ 191 #define CONFIG_FEC_MXC 192 #define CONFIG_FEC_MXC_PHYADDR 0x1f 193 #define CONFIG_MII /* MII PHY management */ 194 195 /* 196 * FPGA 197 */ 198 #define CONFIG_FPGA_COUNT 1 199 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ 200 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 201 #define CONFIG_SYS_FPGA_CHECK_CTRLC 202 #define CONFIG_SYS_FPGA_CHECK_ERROR 203 204 /* 205 * Fuses - IIM 206 */ 207 #ifdef CONFIG_CMD_IMX_FUSE 208 #define IIM_MAC_BANK 0 209 #define IIM_MAC_ROW 5 210 #define IIM0_SCC_KEY 11 211 #define IIM1_SUID 1 212 #endif 213 214 /* 215 * I2C 216 */ 217 218 #ifdef CONFIG_CMD_I2C 219 #define CONFIG_SYS_I2C 220 #define CONFIG_SYS_I2C_MXC 221 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 222 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 223 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ 224 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F 225 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ 226 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F 227 #define CONFIG_SYS_I2C_NOPROBES { } 228 229 #ifdef CONFIG_CMD_EEPROM 230 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ 231 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ 234 #endif /* CONFIG_CMD_EEPROM */ 235 #endif /* CONFIG_CMD_I2C */ 236 237 /* 238 * SD/MMC 239 */ 240 #ifdef CONFIG_CMD_MMC 241 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 242 #endif 243 244 /* 245 * RTC 246 */ 247 #ifdef CONFIG_CMD_DATE 248 #define CONFIG_RTC_DS1374 249 #define CONFIG_SYS_RTC_BUS_NUM 0 250 #endif /* CONFIG_CMD_DATE */ 251 252 /* 253 * PLL 254 * 255 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 256 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| 257 */ 258 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ 259 260 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 261 /* micron 64MB */ 262 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 263 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ 264 #endif 265 266 #if (ACFG_SDRAM_MBYTE_SYZE == 128) 267 /* micron 128MB */ 268 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 269 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ 270 #endif 271 272 #if (ACFG_SDRAM_MBYTE_SYZE == 256) 273 /* micron 256MB */ 274 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ 275 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ 276 #endif 277 278 #endif /* __CONFIG_H */ 279