1 /* 2 * 3 * Configuration settings for the Armadeus Project motherboard APF27 4 * 5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_VERSION_VARIABLE 14 #define CONFIG_ENV_VERSION 10 15 #define CONFIG_IDENT_STRING " apf27 patch 3.10" 16 #define CONFIG_BOARD_NAME apf27 17 18 /* 19 * SoC configurations 20 */ 21 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ 22 #define CONFIG_MACH_TYPE 1698 /* APF27 */ 23 24 /* 25 * Enable the call to miscellaneous platform dependent initialization. 26 */ 27 #define CONFIG_SYS_NO_FLASH 28 29 /* 30 * Board display option 31 */ 32 #define CONFIG_DISPLAY_BOARDINFO 33 #define CONFIG_DISPLAY_CPUINFO 34 35 /* 36 * SPL 37 */ 38 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 39 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 40 #define CONFIG_SPL_MAX_SIZE 2048 41 #define CONFIG_SPL_TEXT_BASE 0xA0000000 42 #define CONFIG_SPL_SERIAL_SUPPORT 43 44 /* NAND boot config */ 45 #define CONFIG_SPL_NAND_SUPPORT 46 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 48 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 50 51 /* 52 * BOOTP options 53 */ 54 #define CONFIG_BOOTP_SUBNETMASK 55 #define CONFIG_BOOTP_GATEWAY 56 #define CONFIG_BOOTP_HOSTNAME 57 #define CONFIG_BOOTP_BOOTPATH 58 #define CONFIG_BOOTP_BOOTFILESIZE 59 #define CONFIG_BOOTP_DNS 60 #define CONFIG_BOOTP_DNS2 61 62 #define CONFIG_HOSTNAME CONFIG_BOARD_NAME 63 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" 64 65 /* 66 * U-Boot Commands 67 */ 68 #define CONFIG_CMD_ASKENV /* ask for env variable */ 69 #define CONFIG_CMD_BSP /* Board Specific functions */ 70 #define CONFIG_CMD_CACHE /* icache, dcache */ 71 #define CONFIG_CMD_DATE 72 #define CONFIG_CMD_DHCP /* DHCP Support */ 73 #define CONFIG_CMD_DNS 74 #define CONFIG_CMD_EEPROM 75 #define CONFIG_CMD_EXT2 76 #define CONFIG_CMD_FAT /* FAT support */ 77 #define CONFIG_CMD_IMX_FUSE /* imx iim fuse */ 78 #define CONFIG_CMD_I2C 79 #define CONFIG_CMD_MII /* MII support */ 80 #define CONFIG_CMD_MMC 81 #define CONFIG_CMD_MTDPARTS /* MTD partition support */ 82 #define CONFIG_CMD_NAND /* NAND support */ 83 #define CONFIG_CMD_NAND_LOCK_UNLOCK 84 #define CONFIG_CMD_NAND_TRIMFFS 85 #define CONFIG_CMD_PING /* ping support */ 86 #define CONFIG_CMD_UBI 87 #define CONFIG_CMD_UBIFS 88 89 /* 90 * Memory configurations 91 */ 92 #define CONFIG_NR_DRAM_POPULATED 1 93 #define CONFIG_NR_DRAM_BANKS 2 94 95 #define ACFG_SDRAM_MBYTE_SYZE 64 96 97 #define PHYS_SDRAM_1 0xA0000000 98 #define PHYS_SDRAM_2 0xB0000000 99 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 100 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) 101 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ 102 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ 103 104 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ 105 + PHYS_SDRAM_1_SIZE - 0x0100000) 106 107 #define CONFIG_SYS_TEXT_BASE 0xA0000800 108 109 /* 110 * FLASH organization 111 */ 112 #define ACFG_MONITOR_OFFSET 0x00000000 113 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ 114 #define CONFIG_ENV_IS_IN_NAND 115 #define CONFIG_ENV_OVERWRITE 116 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ 117 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ 118 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ 119 #define CONFIG_ENV_OFFSET_REDUND \ 120 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ 121 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ 122 #define CONFIG_FIRMWARE_OFFSET 0x00200000 123 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ 124 #define CONFIG_KERNEL_OFFSET 0x00300000 125 #define CONFIG_ROOTFS_OFFSET 0x00800000 126 127 #define CONFIG_MTDMAP "mxc_nand.0" 128 #define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP 129 #define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \ 130 ":1M(u-boot)ro," \ 131 "512K(env)," \ 132 "512K(env2)," \ 133 "512K(firmware)," \ 134 "512K(dtb)," \ 135 "5M(kernel)," \ 136 "-(rootfs)" 137 138 /* 139 * U-Boot general configurations 140 */ 141 #define CONFIG_SYS_LONGHELP 142 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ 143 #define CONFIG_SYS_PBSIZE \ 144 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 145 /* Print buffer size */ 146 #define CONFIG_SYS_MAXARGS 16 /* max command args */ 147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 148 /* Boot argument buffer size */ 149 #define CONFIG_AUTO_COMPLETE 150 #define CONFIG_CMDLINE_EDITING 151 #define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */ 152 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */ 153 #define CONFIG_ENV_VARS_UBOOT_CONFIG 154 #define CONFIG_PREBOOT "run check_flash check_env;" 155 156 157 /* 158 * Boot Linux 159 */ 160 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 161 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 162 #define CONFIG_INITRD_TAG /* send initrd params */ 163 164 #define CONFIG_BOOTDELAY 5 165 #define CONFIG_ZERO_BOOTDELAY_CHECK 166 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" 167 #define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \ 168 __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \ 169 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " 170 171 #define ACFG_CONSOLE_DEV ttySMX0 172 #define CONFIG_BOOTCOMMAND "run ubifsboot" 173 #define CONFIG_SYS_AUTOLOAD "no" 174 /* 175 * Default load address for user programs and kernel 176 */ 177 #define CONFIG_LOADADDR 0xA0000000 178 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 179 180 /* 181 * Extra Environments 182 */ 183 #define CONFIG_EXTRA_ENV_SETTINGS \ 184 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ 185 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ 186 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 187 "partition=nand0,6\0" \ 188 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ 189 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ 190 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ 191 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ 192 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ 193 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ 194 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ 195 "kernel_addr_r=A0000000\0" \ 196 "check_env=if test -n ${flash_env_version}; " \ 197 "then env default env_version; " \ 198 "else env set flash_env_version ${env_version}; env save; "\ 199 "fi; " \ 200 "if itest ${flash_env_version} < ${env_version}; then " \ 201 "echo \"*** Warning - Environment version" \ 202 " change suggests: run flash_reset_env; reset\"; "\ 203 "env default flash_reset_env; "\ 204 "fi; \0" \ 205 "check_flash=nand lock; nand unlock ${env_addr}; \0" \ 206 "flash_reset_env=env default -f -a; saveenv; run update_env;" \ 207 "echo Flash environment variables erased!\0" \ 208 "download_uboot=tftpboot ${loadaddr} ${board_name}" \ 209 "-u-boot-with-spl.bin\0" \ 210 "flash_uboot=nand unlock ${u-boot_addr} ;" \ 211 "nand erase.part u-boot;" \ 212 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ 213 "then nand lock; nand unlock ${env_addr};" \ 214 "echo Flashing of uboot succeed;" \ 215 "else echo Flashing of uboot failed;" \ 216 "fi; \0" \ 217 "update_uboot=run download_uboot flash_uboot\0" \ 218 "download_env=tftpboot ${loadaddr} ${board_name}" \ 219 "-u-boot-env.txt\0" \ 220 "flash_env=env import -t ${loadaddr}; env save; \0" \ 221 "update_env=run download_env flash_env\0" \ 222 "update_all=run update_env update_uboot\0" \ 223 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ 224 225 /* 226 * Serial Driver 227 */ 228 #define CONFIG_MXC_UART 229 #define CONFIG_CONS_INDEX 1 230 #define CONFIG_BAUDRATE 115200 231 #define CONFIG_MXC_UART_BASE UART1_BASE 232 233 /* 234 * GPIO 235 */ 236 #define CONFIG_MXC_GPIO 237 238 /* 239 * NOR 240 */ 241 242 /* 243 * NAND 244 */ 245 #define CONFIG_NAND_MXC 246 247 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 248 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE 249 #define CONFIG_SYS_MAX_NAND_DEVICE 1 250 251 #define CONFIG_MXC_NAND_HWECC 252 #define CONFIG_SYS_NAND_LARGEPAGE 253 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 254 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 255 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 256 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ 257 CONFIG_SYS_NAND_PAGE_SIZE 258 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 259 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 260 #define NAND_MAX_CHIPS 1 261 262 #define CONFIG_FLASH_SHOW_PROGRESS 45 263 #define CONFIG_SYS_NAND_QUIET 1 264 265 /* 266 * Partitions & Filsystems 267 */ 268 #define CONFIG_MTD_DEVICE 269 #define CONFIG_MTD_PARTITIONS 270 #define CONFIG_DOS_PARTITION 271 #define CONFIG_SUPPORT_VFAT 272 273 /* 274 * UBIFS 275 */ 276 #define CONFIG_RBTREE 277 #define CONFIG_LZO 278 279 /* 280 * Ethernet (on SOC imx FEC) 281 */ 282 #define CONFIG_FEC_MXC 283 #define CONFIG_FEC_MXC_PHYADDR 0x1f 284 #define CONFIG_MII /* MII PHY management */ 285 286 /* 287 * FPGA 288 */ 289 #ifndef CONFIG_SPL_BUILD 290 #define CONFIG_FPGA 291 #endif 292 #define CONFIG_FPGA_COUNT 1 293 #define CONFIG_FPGA_XILINX 294 #define CONFIG_FPGA_SPARTAN3 295 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ 296 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 297 #define CONFIG_SYS_FPGA_CHECK_CTRLC 298 #define CONFIG_SYS_FPGA_CHECK_ERROR 299 300 /* 301 * Fuses - IIM 302 */ 303 #ifdef CONFIG_CMD_IMX_FUSE 304 #define IIM_MAC_BANK 0 305 #define IIM_MAC_ROW 5 306 #define IIM0_SCC_KEY 11 307 #define IIM1_SUID 1 308 #endif 309 310 /* 311 * I2C 312 */ 313 314 #ifdef CONFIG_CMD_I2C 315 #define CONFIG_SYS_I2C 316 #define CONFIG_SYS_I2C_MXC 317 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 318 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 319 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ 320 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F 321 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ 322 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F 323 #define CONFIG_SYS_I2C_NOPROBES { } 324 325 #ifdef CONFIG_CMD_EEPROM 326 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ 327 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 328 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 329 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ 330 #endif /* CONFIG_CMD_EEPROM */ 331 #endif /* CONFIG_CMD_I2C */ 332 333 /* 334 * SD/MMC 335 */ 336 #ifdef CONFIG_CMD_MMC 337 #define CONFIG_MMC 338 #define CONFIG_GENERIC_MMC 339 #define CONFIG_MXC_MMC 340 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 341 #endif 342 343 /* 344 * RTC 345 */ 346 #ifdef CONFIG_CMD_DATE 347 #define CONFIG_RTC_DS1374 348 #define CONFIG_SYS_RTC_BUS_NUM 0 349 #endif /* CONFIG_CMD_DATE */ 350 351 /* 352 * PLL 353 * 354 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 355 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| 356 */ 357 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ 358 359 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 360 /* micron 64MB */ 361 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 362 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ 363 #endif 364 365 #if (ACFG_SDRAM_MBYTE_SYZE == 128) 366 /* micron 128MB */ 367 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 368 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ 369 #endif 370 371 #if (ACFG_SDRAM_MBYTE_SYZE == 256) 372 /* micron 256MB */ 373 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ 374 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ 375 #endif 376 377 #endif /* __CONFIG_H */ 378