1 /* 2 * Configuation settings for the Alpha Project AP-SH4A-4A board 3 * 4 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __AP_SH4A_4A_H 10 #define __AP_SH4A_4A_H 11 12 #define CONFIG_CPU_SH7734 1 13 #define CONFIG_400MHZ_MODE 1 14 15 #define CONFIG_SYS_TEXT_BASE 0x8BFC0000 16 17 #define CONFIG_DISPLAY_BOARDINFO 18 #undef CONFIG_SHOW_BOOT_PROGRESS 19 20 /* Ether */ 21 #define CONFIG_SH_ETHER 1 22 #define CONFIG_SH_ETHER_USE_PORT (0) 23 #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 24 #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII) 25 #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */ 26 #define CONFIG_BITBANGMII 27 #define CONFIG_BITBANGMII_MULTI 28 29 /* undef to save memory */ 30 #define CONFIG_SYS_LONGHELP 31 /* Monitor Command Prompt */ 32 /* Buffer size for Console output */ 33 #define CONFIG_SYS_PBSIZE 256 34 /* List of legal baudrate settings for this board */ 35 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 36 37 /* SCIF */ 38 #define CONFIG_SCIF 1 39 #define CONFIG_CONS_SCIF4 1 40 41 /* Suppress display of console information at boot */ 42 43 /* SDRAM */ 44 #define CONFIG_SYS_SDRAM_BASE (0x88000000) 45 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 46 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 47 48 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 49 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE) 50 /* Enable alternate, more extensive, memory test */ 51 #undef CONFIG_SYS_ALT_MEMTEST 52 /* Scratch address used by the alternate memory test */ 53 #undef CONFIG_SYS_MEMTEST_SCRATCH 54 55 /* Enable temporary baudrate change while serial download */ 56 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 57 58 /* FLASH */ 59 #define CONFIG_FLASH_CFI_DRIVER 1 60 #define CONFIG_SYS_FLASH_CFI 61 #undef CONFIG_SYS_FLASH_QUIET_TEST 62 #define CONFIG_SYS_FLASH_EMPTY_INFO 63 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 64 #define CONFIG_SYS_MAX_FLASH_SECT 512 65 66 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 67 #define CONFIG_SYS_MAX_FLASH_BANKS 1 68 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 69 70 /* Timeout for Flash erase operations (in ms) */ 71 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 72 /* Timeout for Flash write operations (in ms) */ 73 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 74 /* Timeout for Flash set sector lock bit operations (in ms) */ 75 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 76 /* Timeout for Flash clear lock bit operations (in ms) */ 77 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 78 79 /* 80 * Use hardware flash sectors protection instead 81 * of U-Boot software protection 82 */ 83 #undef CONFIG_SYS_FLASH_PROTECTION 84 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 85 86 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 87 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 88 /* Monitor size */ 89 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 90 /* Size of DRAM reserved for malloc() use */ 91 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 92 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 93 94 /* ENV setting */ 95 #define CONFIG_ENV_OVERWRITE 1 96 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 97 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 98 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 99 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 100 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 101 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 102 103 /* Board Clock */ 104 #if defined(CONFIG_400MHZ_MODE) 105 #define CONFIG_SYS_CLK_FREQ 50000000 106 #else 107 #define CONFIG_SYS_CLK_FREQ 44444444 108 #endif 109 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 110 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 111 #define CONFIG_SYS_TMU_CLK_DIV 4 112 113 #endif /* __AP_SH4A_4A_H */ 114