xref: /openbmc/u-boot/include/configs/ap_sh4a_4a.h (revision dfb42fc9)
1 /*
2  * Configuation settings for the Alpha Project AP-SH4A-4A board
3  *
4  * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __AP_SH4A_4A_H
10 #define __AP_SH4A_4A_H
11 
12 #undef DEBUG
13 #define CONFIG_CPU_SH7734	1
14 #define CONFIG_AP_SH4A_4A	1
15 #define CONFIG_400MHZ_MODE	1
16 /* #define CONFIG_533MHZ_MODE	1 */
17 
18 #define CONFIG_BOARD_LATE_INIT
19 #define CONFIG_SYS_TEXT_BASE 0x8BFC0000
20 
21 #define CONFIG_CMD_FLASH
22 #define CONFIG_CMD_MEMORY
23 #define CONFIG_CMD_NET
24 #define CONFIG_CMD_PING
25 #define CONFIG_CMD_MII
26 #define CONFIG_CMD_NFS
27 #define CONFIG_CMD_SDRAM
28 #define CONFIG_CMD_ENV
29 #define CONFIG_CMD_SAVEENV
30 
31 #define CONFIG_BAUDRATE		115200
32 #define CONFIG_BOOTDELAY	3
33 #define CONFIG_BOOTARGS		"console=ttySC4,115200"
34 
35 #define CONFIG_VERSION_VARIABLE
36 #undef  CONFIG_SHOW_BOOT_PROGRESS
37 
38 /* Ether */
39 #define CONFIG_SH_ETHER 1
40 #define CONFIG_SH_ETHER_USE_PORT (0)
41 #define CONFIG_SH_ETHER_PHY_ADDR (0x0)
42 #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
43 #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */
44 #define CONFIG_PHYLIB
45 #define CONFIG_PHY_MICREL 1
46 #define CONFIG_BITBANGMII
47 #define CONFIG_BITBANGMII_MULTI
48 
49 /* I2C */
50 #define CONFIG_CMD_I2C
51 #define CONFIG_SH_SH7734_I2C	1
52 #define CONFIG_HARD_I2C			1
53 #define CONFIG_I2C_MULTI_BUS	1
54 #define CONFIG_SYS_MAX_I2C_BUS	2
55 #define CONFIG_SYS_I2C_MODULE	0
56 #define CONFIG_SYS_I2C_SPEED	400000 /* 400 kHz */
57 #define CONFIG_SYS_I2C_SLAVE	0x50
58 #define CONFIG_SH_I2C_DATA_HIGH	4
59 #define CONFIG_SH_I2C_DATA_LOW	5
60 #define CONFIG_SH_I2C_CLOCK		500000000
61 #define CONFIG_SH_I2C_BASE0		0xFFC70000
62 #define CONFIG_SH_I2C_BASE1		0xFFC71000
63 
64 /* undef to save memory	*/
65 #define CONFIG_SYS_LONGHELP
66 /* Monitor Command Prompt */
67 /* Buffer size for input from the Console */
68 #define CONFIG_SYS_CBSIZE		256
69 /* Buffer size for Console output */
70 #define CONFIG_SYS_PBSIZE		256
71 /* max args accepted for monitor commands */
72 #define CONFIG_SYS_MAXARGS		16
73 /* Buffer size for Boot Arguments passed to kernel */
74 #define CONFIG_SYS_BARGSIZE	512
75 /* List of legal baudrate settings for this board */
76 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
77 
78 /* SCIF */
79 #define CONFIG_SCIF_CONSOLE	1
80 #define CONFIG_SCIF			1
81 #define CONFIG_CONS_SCIF4	1
82 
83 /* Suppress display of console information at boot */
84 #undef  CONFIG_SYS_CONSOLE_INFO_QUIET
85 #undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
86 #undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
87 
88 /* SDRAM */
89 #define CONFIG_SYS_SDRAM_BASE	(0x88000000)
90 #define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)
91 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
92 
93 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
94 #define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE)
95 /* Enable alternate, more extensive, memory test */
96 #undef  CONFIG_SYS_ALT_MEMTEST
97 /* Scratch address used by the alternate memory test */
98 #undef  CONFIG_SYS_MEMTEST_SCRATCH
99 
100 /* Enable temporary baudrate change while serial download */
101 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
102 
103 /* FLASH */
104 #define CONFIG_FLASH_CFI_DRIVER 1
105 #define CONFIG_SYS_FLASH_CFI
106 #undef  CONFIG_SYS_FLASH_QUIET_TEST
107 #define CONFIG_SYS_FLASH_EMPTY_INFO
108 #define CONFIG_SYS_FLASH_BASE	(0xA0000000)
109 #define CONFIG_SYS_MAX_FLASH_SECT	512
110 
111 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
112 #define CONFIG_SYS_MAX_FLASH_BANKS	1
113 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
114 
115 /* Timeout for Flash erase operations (in ms) */
116 #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
117 /* Timeout for Flash write operations (in ms) */
118 #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
119 /* Timeout for Flash set sector lock bit operations (in ms) */
120 #define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
121 /* Timeout for Flash clear lock bit operations (in ms) */
122 #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
123 
124 /*
125  * Use hardware flash sectors protection instead
126  * of U-Boot software protection
127  */
128 #undef  CONFIG_SYS_FLASH_PROTECTION
129 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
130 
131 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
132 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
133 /* Monitor size */
134 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
135 /* Size of DRAM reserved for malloc() use */
136 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
137 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
138 
139 /* ENV setting */
140 #define CONFIG_ENV_IS_IN_FLASH
141 #define CONFIG_ENV_OVERWRITE	1
142 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
143 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
144 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
145 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
146 #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
147 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
148 
149 /* Board Clock */
150 #if defined(CONFIG_400MHZ_MODE)
151 #define CONFIG_SYS_CLK_FREQ 50000000
152 #else
153 #define CONFIG_SYS_CLK_FREQ 44444444
154 #endif
155 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
156 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
157 #define CONFIG_SYS_TMU_CLK_DIV      4
158 
159 #endif	/* __AP_SH4A_4A_H */
160