1 /* 2 * Configuation settings for the Alpha Project AP-SH4A-4A board 3 * 4 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __AP_SH4A_4A_H 10 #define __AP_SH4A_4A_H 11 12 #define CONFIG_CPU_SH7734 1 13 #define CONFIG_AP_SH4A_4A 1 14 #define CONFIG_400MHZ_MODE 1 15 /* #define CONFIG_533MHZ_MODE 1 */ 16 17 #define CONFIG_SYS_TEXT_BASE 0x8BFC0000 18 19 #define CONFIG_DISPLAY_BOARDINFO 20 #undef CONFIG_SHOW_BOOT_PROGRESS 21 22 /* Ether */ 23 #define CONFIG_SH_ETHER 1 24 #define CONFIG_SH_ETHER_USE_PORT (0) 25 #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 26 #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII) 27 #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */ 28 #define CONFIG_BITBANGMII 29 #define CONFIG_BITBANGMII_MULTI 30 31 /* undef to save memory */ 32 #define CONFIG_SYS_LONGHELP 33 /* Monitor Command Prompt */ 34 /* Buffer size for input from the Console */ 35 #define CONFIG_SYS_CBSIZE 256 36 /* Buffer size for Console output */ 37 #define CONFIG_SYS_PBSIZE 256 38 /* max args accepted for monitor commands */ 39 #define CONFIG_SYS_MAXARGS 16 40 /* Buffer size for Boot Arguments passed to kernel */ 41 #define CONFIG_SYS_BARGSIZE 512 42 /* List of legal baudrate settings for this board */ 43 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 44 45 /* SCIF */ 46 #define CONFIG_SCIF 1 47 #define CONFIG_CONS_SCIF4 1 48 49 /* Suppress display of console information at boot */ 50 51 /* SDRAM */ 52 #define CONFIG_SYS_SDRAM_BASE (0x88000000) 53 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 54 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 55 56 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 57 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE) 58 /* Enable alternate, more extensive, memory test */ 59 #undef CONFIG_SYS_ALT_MEMTEST 60 /* Scratch address used by the alternate memory test */ 61 #undef CONFIG_SYS_MEMTEST_SCRATCH 62 63 /* Enable temporary baudrate change while serial download */ 64 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 65 66 /* FLASH */ 67 #define CONFIG_FLASH_CFI_DRIVER 1 68 #define CONFIG_SYS_FLASH_CFI 69 #undef CONFIG_SYS_FLASH_QUIET_TEST 70 #define CONFIG_SYS_FLASH_EMPTY_INFO 71 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 72 #define CONFIG_SYS_MAX_FLASH_SECT 512 73 74 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 75 #define CONFIG_SYS_MAX_FLASH_BANKS 1 76 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 77 78 /* Timeout for Flash erase operations (in ms) */ 79 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 80 /* Timeout for Flash write operations (in ms) */ 81 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 82 /* Timeout for Flash set sector lock bit operations (in ms) */ 83 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 84 /* Timeout for Flash clear lock bit operations (in ms) */ 85 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 86 87 /* 88 * Use hardware flash sectors protection instead 89 * of U-Boot software protection 90 */ 91 #undef CONFIG_SYS_FLASH_PROTECTION 92 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 93 94 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 95 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 96 /* Monitor size */ 97 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 98 /* Size of DRAM reserved for malloc() use */ 99 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 100 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 101 102 /* ENV setting */ 103 #define CONFIG_ENV_OVERWRITE 1 104 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 105 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 106 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 107 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 108 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 109 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 110 111 /* Board Clock */ 112 #if defined(CONFIG_400MHZ_MODE) 113 #define CONFIG_SYS_CLK_FREQ 50000000 114 #else 115 #define CONFIG_SYS_CLK_FREQ 44444444 116 #endif 117 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 118 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 119 #define CONFIG_SYS_TMU_CLK_DIV 4 120 121 #endif /* __AP_SH4A_4A_H */ 122