1*bfc93fb4SNobuhiro Iwamatsu /* 2*bfc93fb4SNobuhiro Iwamatsu * Configuation settings for the Alpha Project AP-SH4A-4A board 3*bfc93fb4SNobuhiro Iwamatsu * 4*bfc93fb4SNobuhiro Iwamatsu * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5*bfc93fb4SNobuhiro Iwamatsu * 6*bfc93fb4SNobuhiro Iwamatsu * See file CREDITS for list of people who contributed to this 7*bfc93fb4SNobuhiro Iwamatsu * project. 8*bfc93fb4SNobuhiro Iwamatsu * 9*bfc93fb4SNobuhiro Iwamatsu * This program is free software; you can redistribute it and/or 10*bfc93fb4SNobuhiro Iwamatsu * modify it under the terms of the GNU General Public License as 11*bfc93fb4SNobuhiro Iwamatsu * published by the Free Software Foundation; either version 2 of 12*bfc93fb4SNobuhiro Iwamatsu * the License, or (at your option) any later version. 13*bfc93fb4SNobuhiro Iwamatsu * 14*bfc93fb4SNobuhiro Iwamatsu * This program is distributed in the hope that it will be useful, 15*bfc93fb4SNobuhiro Iwamatsu * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*bfc93fb4SNobuhiro Iwamatsu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*bfc93fb4SNobuhiro Iwamatsu * GNU General Public License for more details. 18*bfc93fb4SNobuhiro Iwamatsu * 19*bfc93fb4SNobuhiro Iwamatsu */ 20*bfc93fb4SNobuhiro Iwamatsu 21*bfc93fb4SNobuhiro Iwamatsu #ifndef __AP_SH4A_4A_H 22*bfc93fb4SNobuhiro Iwamatsu #define __AP_SH4A_4A_H 23*bfc93fb4SNobuhiro Iwamatsu 24*bfc93fb4SNobuhiro Iwamatsu #undef DEBUG 25*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH 1 26*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH4 1 27*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH4A 1 28*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CPU_SH7734 1 29*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_AP_SH4A_4A 1 30*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_400MHZ_MODE 1 31*bfc93fb4SNobuhiro Iwamatsu /* #define CONFIG_533MHZ_MODE 1 */ 32*bfc93fb4SNobuhiro Iwamatsu 33*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BOARD_LATE_INIT 34*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0x8BFC0000 35*bfc93fb4SNobuhiro Iwamatsu 36*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_FLASH 37*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_MEMORY 38*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_NET 39*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_PING 40*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_MII 41*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_NFS 42*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_SDRAM 43*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_ENV 44*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_SAVEENV 45*bfc93fb4SNobuhiro Iwamatsu 46*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BAUDRATE 115200 47*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BOOTDELAY 3 48*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BOOTARGS "console=ttySC4,115200" 49*bfc93fb4SNobuhiro Iwamatsu 50*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_VERSION_VARIABLE 51*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 52*bfc93fb4SNobuhiro Iwamatsu 53*bfc93fb4SNobuhiro Iwamatsu /* Ether */ 54*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER 1 55*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_USE_PORT (0) 56*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 57*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII) 58*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */ 59*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_PHYLIB 60*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_PHY_MICREL 1 61*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BITBANGMII 62*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BITBANGMII_MULTI 63*bfc93fb4SNobuhiro Iwamatsu 64*bfc93fb4SNobuhiro Iwamatsu /* I2C */ 65*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_I2C 66*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_SH7734_I2C 1 67*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_HARD_I2C 1 68*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_I2C_MULTI_BUS 1 69*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAX_I2C_BUS 2 70*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_MODULE 0 71*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SPEED 400000 /* 400 kHz */ 72*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SLAVE 0x50 73*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_HIGH 4 74*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_LOW 5 75*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_CLOCK 500000000 76*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_BASE0 0xFFC70000 77*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_BASE1 0xFFC71000 78*bfc93fb4SNobuhiro Iwamatsu 79*bfc93fb4SNobuhiro Iwamatsu /* undef to save memory */ 80*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_LONGHELP 81*bfc93fb4SNobuhiro Iwamatsu /* Monitor Command Prompt */ 82*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_PROMPT "=> " 83*bfc93fb4SNobuhiro Iwamatsu /* Buffer size for input from the Console */ 84*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_CBSIZE 256 85*bfc93fb4SNobuhiro Iwamatsu /* Buffer size for Console output */ 86*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_PBSIZE 256 87*bfc93fb4SNobuhiro Iwamatsu /* max args accepted for monitor commands */ 88*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAXARGS 16 89*bfc93fb4SNobuhiro Iwamatsu /* Buffer size for Boot Arguments passed to kernel */ 90*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_BARGSIZE 512 91*bfc93fb4SNobuhiro Iwamatsu /* List of legal baudrate settings for this board */ 92*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 93*bfc93fb4SNobuhiro Iwamatsu 94*bfc93fb4SNobuhiro Iwamatsu /* SCIF */ 95*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE 1 96*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SCIF 1 97*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CONS_SCIF4 1 98*bfc93fb4SNobuhiro Iwamatsu 99*bfc93fb4SNobuhiro Iwamatsu /* Suppress display of console information at boot */ 100*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_CONSOLE_INFO_QUIET 101*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 102*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 103*bfc93fb4SNobuhiro Iwamatsu 104*bfc93fb4SNobuhiro Iwamatsu /* SDRAM */ 105*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_BASE (0x88000000) 106*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 107*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 108*bfc93fb4SNobuhiro Iwamatsu 109*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 110*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE) 111*bfc93fb4SNobuhiro Iwamatsu /* Enable alternate, more extensive, memory test */ 112*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_ALT_MEMTEST 113*bfc93fb4SNobuhiro Iwamatsu /* Scratch address used by the alternate memory test */ 114*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_MEMTEST_SCRATCH 115*bfc93fb4SNobuhiro Iwamatsu 116*bfc93fb4SNobuhiro Iwamatsu /* Enable temporary baudrate change while serial download */ 117*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_LOADS_BAUD_CHANGE 118*bfc93fb4SNobuhiro Iwamatsu 119*bfc93fb4SNobuhiro Iwamatsu /* FLASH */ 120*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_FLASH_CFI_DRIVER 1 121*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_CFI 122*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_FLASH_QUIET_TEST 123*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_EMPTY_INFO 124*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_BASE (0xA0000000) 125*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAX_FLASH_SECT 512 126*bfc93fb4SNobuhiro Iwamatsu 127*bfc93fb4SNobuhiro Iwamatsu /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 128*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAX_FLASH_BANKS 1 129*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 130*bfc93fb4SNobuhiro Iwamatsu 131*bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash erase operations (in ms) */ 132*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 133*bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash write operations (in ms) */ 134*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 135*bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash set sector lock bit operations (in ms) */ 136*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 137*bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash clear lock bit operations (in ms) */ 138*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 139*bfc93fb4SNobuhiro Iwamatsu 140*bfc93fb4SNobuhiro Iwamatsu /* 141*bfc93fb4SNobuhiro Iwamatsu * Use hardware flash sectors protection instead 142*bfc93fb4SNobuhiro Iwamatsu * of U-Boot software protection 143*bfc93fb4SNobuhiro Iwamatsu */ 144*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_FLASH_PROTECTION 145*bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_DIRECT_FLASH_TFTP 146*bfc93fb4SNobuhiro Iwamatsu 147*bfc93fb4SNobuhiro Iwamatsu /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 148*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 149*bfc93fb4SNobuhiro Iwamatsu /* Monitor size */ 150*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 151*bfc93fb4SNobuhiro Iwamatsu /* Size of DRAM reserved for malloc() use */ 152*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 153*bfc93fb4SNobuhiro Iwamatsu /* size in bytes reserved for initial data */ 154*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_GBL_DATA_SIZE (256) 155*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 156*bfc93fb4SNobuhiro Iwamatsu 157*bfc93fb4SNobuhiro Iwamatsu /* ENV setting */ 158*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_IS_IN_FLASH 159*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE 1 160*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_SECT_SIZE (128 * 1024) 161*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 162*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 163*bfc93fb4SNobuhiro Iwamatsu /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 164*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 165*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 166*bfc93fb4SNobuhiro Iwamatsu 167*bfc93fb4SNobuhiro Iwamatsu /* Board Clock */ 168*bfc93fb4SNobuhiro Iwamatsu #if defined(CONFIG_400MHZ_MODE) 169*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 50000000 170*bfc93fb4SNobuhiro Iwamatsu #else 171*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 44444444 172*bfc93fb4SNobuhiro Iwamatsu #endif 173*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_TMU_CLK_DIV 4 174*bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_HZ 1000 175*bfc93fb4SNobuhiro Iwamatsu 176*bfc93fb4SNobuhiro Iwamatsu #endif /* __AP_SH4A_4A_H */ 177