1bfc93fb4SNobuhiro Iwamatsu /* 2bfc93fb4SNobuhiro Iwamatsu * Configuation settings for the Alpha Project AP-SH4A-4A board 3bfc93fb4SNobuhiro Iwamatsu * 4bfc93fb4SNobuhiro Iwamatsu * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5bfc93fb4SNobuhiro Iwamatsu * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7bfc93fb4SNobuhiro Iwamatsu */ 8bfc93fb4SNobuhiro Iwamatsu 9bfc93fb4SNobuhiro Iwamatsu #ifndef __AP_SH4A_4A_H 10bfc93fb4SNobuhiro Iwamatsu #define __AP_SH4A_4A_H 11bfc93fb4SNobuhiro Iwamatsu 12bfc93fb4SNobuhiro Iwamatsu #undef DEBUG 13bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH 1 14bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH4 1 15bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH4A 1 16bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CPU_SH7734 1 17bfc93fb4SNobuhiro Iwamatsu #define CONFIG_AP_SH4A_4A 1 18bfc93fb4SNobuhiro Iwamatsu #define CONFIG_400MHZ_MODE 1 19bfc93fb4SNobuhiro Iwamatsu /* #define CONFIG_533MHZ_MODE 1 */ 20bfc93fb4SNobuhiro Iwamatsu 21bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BOARD_LATE_INIT 22bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0x8BFC0000 23bfc93fb4SNobuhiro Iwamatsu 24bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_FLASH 25bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_MEMORY 26bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_NET 27bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_PING 28bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_MII 29bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_NFS 30bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_SDRAM 31bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_ENV 32bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_SAVEENV 33bfc93fb4SNobuhiro Iwamatsu 34bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BAUDRATE 115200 35bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BOOTDELAY 3 36bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BOOTARGS "console=ttySC4,115200" 37bfc93fb4SNobuhiro Iwamatsu 38bfc93fb4SNobuhiro Iwamatsu #define CONFIG_VERSION_VARIABLE 39bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 40bfc93fb4SNobuhiro Iwamatsu 41bfc93fb4SNobuhiro Iwamatsu /* Ether */ 42bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER 1 43bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_USE_PORT (0) 44bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 45bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII) 46bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */ 47bfc93fb4SNobuhiro Iwamatsu #define CONFIG_PHYLIB 48bfc93fb4SNobuhiro Iwamatsu #define CONFIG_PHY_MICREL 1 49bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BITBANGMII 50bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BITBANGMII_MULTI 51bfc93fb4SNobuhiro Iwamatsu 52bfc93fb4SNobuhiro Iwamatsu /* I2C */ 53bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CMD_I2C 54bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_SH7734_I2C 1 55bfc93fb4SNobuhiro Iwamatsu #define CONFIG_HARD_I2C 1 56bfc93fb4SNobuhiro Iwamatsu #define CONFIG_I2C_MULTI_BUS 1 57bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAX_I2C_BUS 2 58bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_MODULE 0 59bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SPEED 400000 /* 400 kHz */ 60bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SLAVE 0x50 61bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_HIGH 4 62bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_LOW 5 63bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_CLOCK 500000000 64bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_BASE0 0xFFC70000 65bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_I2C_BASE1 0xFFC71000 66bfc93fb4SNobuhiro Iwamatsu 67bfc93fb4SNobuhiro Iwamatsu /* undef to save memory */ 68bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_LONGHELP 69bfc93fb4SNobuhiro Iwamatsu /* Monitor Command Prompt */ 70bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_PROMPT "=> " 71bfc93fb4SNobuhiro Iwamatsu /* Buffer size for input from the Console */ 72bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_CBSIZE 256 73bfc93fb4SNobuhiro Iwamatsu /* Buffer size for Console output */ 74bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_PBSIZE 256 75bfc93fb4SNobuhiro Iwamatsu /* max args accepted for monitor commands */ 76bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAXARGS 16 77bfc93fb4SNobuhiro Iwamatsu /* Buffer size for Boot Arguments passed to kernel */ 78bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_BARGSIZE 512 79bfc93fb4SNobuhiro Iwamatsu /* List of legal baudrate settings for this board */ 80bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 81bfc93fb4SNobuhiro Iwamatsu 82bfc93fb4SNobuhiro Iwamatsu /* SCIF */ 83bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE 1 84bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SCIF 1 85bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CONS_SCIF4 1 86bfc93fb4SNobuhiro Iwamatsu 87bfc93fb4SNobuhiro Iwamatsu /* Suppress display of console information at boot */ 88bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_CONSOLE_INFO_QUIET 89bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 90bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 91bfc93fb4SNobuhiro Iwamatsu 92bfc93fb4SNobuhiro Iwamatsu /* SDRAM */ 93bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_BASE (0x88000000) 94bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 95bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 96bfc93fb4SNobuhiro Iwamatsu 97bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 98bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE) 99bfc93fb4SNobuhiro Iwamatsu /* Enable alternate, more extensive, memory test */ 100bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_ALT_MEMTEST 101bfc93fb4SNobuhiro Iwamatsu /* Scratch address used by the alternate memory test */ 102bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_MEMTEST_SCRATCH 103bfc93fb4SNobuhiro Iwamatsu 104bfc93fb4SNobuhiro Iwamatsu /* Enable temporary baudrate change while serial download */ 105bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_LOADS_BAUD_CHANGE 106bfc93fb4SNobuhiro Iwamatsu 107bfc93fb4SNobuhiro Iwamatsu /* FLASH */ 108bfc93fb4SNobuhiro Iwamatsu #define CONFIG_FLASH_CFI_DRIVER 1 109bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_CFI 110bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_FLASH_QUIET_TEST 111bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_EMPTY_INFO 112bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_BASE (0xA0000000) 113bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAX_FLASH_SECT 512 114bfc93fb4SNobuhiro Iwamatsu 115bfc93fb4SNobuhiro Iwamatsu /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 116bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAX_FLASH_BANKS 1 117bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 118bfc93fb4SNobuhiro Iwamatsu 119bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash erase operations (in ms) */ 120bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 121bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash write operations (in ms) */ 122bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 123bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash set sector lock bit operations (in ms) */ 124bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 125bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash clear lock bit operations (in ms) */ 126bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 127bfc93fb4SNobuhiro Iwamatsu 128bfc93fb4SNobuhiro Iwamatsu /* 129bfc93fb4SNobuhiro Iwamatsu * Use hardware flash sectors protection instead 130bfc93fb4SNobuhiro Iwamatsu * of U-Boot software protection 131bfc93fb4SNobuhiro Iwamatsu */ 132bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_FLASH_PROTECTION 133bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_DIRECT_FLASH_TFTP 134bfc93fb4SNobuhiro Iwamatsu 135bfc93fb4SNobuhiro Iwamatsu /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 136bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 137bfc93fb4SNobuhiro Iwamatsu /* Monitor size */ 138bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 139bfc93fb4SNobuhiro Iwamatsu /* Size of DRAM reserved for malloc() use */ 140bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 141bfc93fb4SNobuhiro Iwamatsu /* size in bytes reserved for initial data */ 142bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_GBL_DATA_SIZE (256) 143bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 144bfc93fb4SNobuhiro Iwamatsu 145bfc93fb4SNobuhiro Iwamatsu /* ENV setting */ 146bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_IS_IN_FLASH 147bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE 1 148bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_SECT_SIZE (128 * 1024) 149bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 150bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 151bfc93fb4SNobuhiro Iwamatsu /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 152bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 153bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 154bfc93fb4SNobuhiro Iwamatsu 155bfc93fb4SNobuhiro Iwamatsu /* Board Clock */ 156bfc93fb4SNobuhiro Iwamatsu #if defined(CONFIG_400MHZ_MODE) 157bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 50000000 158bfc93fb4SNobuhiro Iwamatsu #else 159bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 44444444 160bfc93fb4SNobuhiro Iwamatsu #endif 161*684a501eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 162*684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 163bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_TMU_CLK_DIV 4 164bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_HZ 1000 165bfc93fb4SNobuhiro Iwamatsu 166bfc93fb4SNobuhiro Iwamatsu #endif /* __AP_SH4A_4A_H */ 167