1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2bfc93fb4SNobuhiro Iwamatsu /* 3bfc93fb4SNobuhiro Iwamatsu * Configuation settings for the Alpha Project AP-SH4A-4A board 4bfc93fb4SNobuhiro Iwamatsu * 5bfc93fb4SNobuhiro Iwamatsu * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 6bfc93fb4SNobuhiro Iwamatsu */ 7bfc93fb4SNobuhiro Iwamatsu 8bfc93fb4SNobuhiro Iwamatsu #ifndef __AP_SH4A_4A_H 9bfc93fb4SNobuhiro Iwamatsu #define __AP_SH4A_4A_H 10bfc93fb4SNobuhiro Iwamatsu 11bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CPU_SH7734 1 12bfc93fb4SNobuhiro Iwamatsu #define CONFIG_400MHZ_MODE 1 13bfc93fb4SNobuhiro Iwamatsu 1418a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 15bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 16bfc93fb4SNobuhiro Iwamatsu 17bfc93fb4SNobuhiro Iwamatsu /* Ether */ 18bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_USE_PORT (0) 19bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 20bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII) 21bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */ 22bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BITBANGMII 23bfc93fb4SNobuhiro Iwamatsu #define CONFIG_BITBANGMII_MULTI 24bfc93fb4SNobuhiro Iwamatsu 25bfc93fb4SNobuhiro Iwamatsu /* undef to save memory */ 26bfc93fb4SNobuhiro Iwamatsu /* Monitor Command Prompt */ 27bfc93fb4SNobuhiro Iwamatsu /* Buffer size for Console output */ 28bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_PBSIZE 256 29bfc93fb4SNobuhiro Iwamatsu /* List of legal baudrate settings for this board */ 30bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 31bfc93fb4SNobuhiro Iwamatsu 32bfc93fb4SNobuhiro Iwamatsu /* SCIF */ 33bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SCIF 1 34bfc93fb4SNobuhiro Iwamatsu #define CONFIG_CONS_SCIF4 1 35bfc93fb4SNobuhiro Iwamatsu 36bfc93fb4SNobuhiro Iwamatsu /* Suppress display of console information at boot */ 37bfc93fb4SNobuhiro Iwamatsu 38bfc93fb4SNobuhiro Iwamatsu /* SDRAM */ 39bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_BASE (0x88000000) 40bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 41bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 42bfc93fb4SNobuhiro Iwamatsu 43bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 44bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE) 45bfc93fb4SNobuhiro Iwamatsu /* Enable alternate, more extensive, memory test */ 46bfc93fb4SNobuhiro Iwamatsu /* Scratch address used by the alternate memory test */ 47bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_MEMTEST_SCRATCH 48bfc93fb4SNobuhiro Iwamatsu 49bfc93fb4SNobuhiro Iwamatsu /* Enable temporary baudrate change while serial download */ 50bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_LOADS_BAUD_CHANGE 51bfc93fb4SNobuhiro Iwamatsu 52bfc93fb4SNobuhiro Iwamatsu /* FLASH */ 53bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_FLASH_QUIET_TEST 54bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_EMPTY_INFO 55bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_BASE (0xA0000000) 56bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAX_FLASH_SECT 512 57bfc93fb4SNobuhiro Iwamatsu 58bfc93fb4SNobuhiro Iwamatsu /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 59bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MAX_FLASH_BANKS 1 60bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 61bfc93fb4SNobuhiro Iwamatsu 62bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash erase operations (in ms) */ 63bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 64bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash write operations (in ms) */ 65bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 66bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash set sector lock bit operations (in ms) */ 67bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 68bfc93fb4SNobuhiro Iwamatsu /* Timeout for Flash clear lock bit operations (in ms) */ 69bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 70bfc93fb4SNobuhiro Iwamatsu 71bfc93fb4SNobuhiro Iwamatsu /* 72bfc93fb4SNobuhiro Iwamatsu * Use hardware flash sectors protection instead 73bfc93fb4SNobuhiro Iwamatsu * of U-Boot software protection 74bfc93fb4SNobuhiro Iwamatsu */ 75bfc93fb4SNobuhiro Iwamatsu #undef CONFIG_SYS_DIRECT_FLASH_TFTP 76bfc93fb4SNobuhiro Iwamatsu 77bfc93fb4SNobuhiro Iwamatsu /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 78bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 79bfc93fb4SNobuhiro Iwamatsu /* Monitor size */ 80bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 81bfc93fb4SNobuhiro Iwamatsu /* Size of DRAM reserved for malloc() use */ 82bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 83bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 84bfc93fb4SNobuhiro Iwamatsu 85bfc93fb4SNobuhiro Iwamatsu /* ENV setting */ 86bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE 1 87bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_SECT_SIZE (128 * 1024) 88bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 89bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 90bfc93fb4SNobuhiro Iwamatsu /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 91bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 92bfc93fb4SNobuhiro Iwamatsu #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 93bfc93fb4SNobuhiro Iwamatsu 94bfc93fb4SNobuhiro Iwamatsu /* Board Clock */ 95bfc93fb4SNobuhiro Iwamatsu #if defined(CONFIG_400MHZ_MODE) 96bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 50000000 97bfc93fb4SNobuhiro Iwamatsu #else 98bfc93fb4SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 44444444 99bfc93fb4SNobuhiro Iwamatsu #endif 100684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 101bfc93fb4SNobuhiro Iwamatsu 102bfc93fb4SNobuhiro Iwamatsu #endif /* __AP_SH4A_4A_H */ 103