xref: /openbmc/u-boot/include/configs/ap325rxa.h (revision 8dd29c87)
16f0da497SNobuhiro Iwamatsu /*
26f0da497SNobuhiro Iwamatsu  * Configuation settings for the Renesas Solutions AP-325RXA board
36f0da497SNobuhiro Iwamatsu  *
46f0da497SNobuhiro Iwamatsu  * Copyright (C) 2008 Renesas Solutions Corp.
56f0da497SNobuhiro Iwamatsu  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
66f0da497SNobuhiro Iwamatsu  *
76f0da497SNobuhiro Iwamatsu  * See file CREDITS for list of people who contributed to this
86f0da497SNobuhiro Iwamatsu  * project.
96f0da497SNobuhiro Iwamatsu  *
106f0da497SNobuhiro Iwamatsu  * This program is free software; you can redistribute it and/or
116f0da497SNobuhiro Iwamatsu  * modify it under the terms of the GNU General Public License as
126f0da497SNobuhiro Iwamatsu  * published by the Free Software Foundation; either version 2 of
136f0da497SNobuhiro Iwamatsu  * the License, or (at your option) any later version.
146f0da497SNobuhiro Iwamatsu  *
156f0da497SNobuhiro Iwamatsu  * This program is distributed in the hope that it will be useful,
166f0da497SNobuhiro Iwamatsu  * but WITHOUT ANY WARRANTY; without even the implied warranty of
176f0da497SNobuhiro Iwamatsu  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
186f0da497SNobuhiro Iwamatsu  * GNU General Public License for more details.
196f0da497SNobuhiro Iwamatsu  *
206f0da497SNobuhiro Iwamatsu  * You should have received a copy of the GNU General Public License
216f0da497SNobuhiro Iwamatsu  * along with this program; if not, write to the Free Software
226f0da497SNobuhiro Iwamatsu  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
236f0da497SNobuhiro Iwamatsu  * MA 02111-1307 USA
246f0da497SNobuhiro Iwamatsu  */
256f0da497SNobuhiro Iwamatsu 
266f0da497SNobuhiro Iwamatsu #ifndef __AP325RXA_H
276f0da497SNobuhiro Iwamatsu #define __AP325RXA_H
286f0da497SNobuhiro Iwamatsu 
296f0da497SNobuhiro Iwamatsu #undef DEBUG
306f0da497SNobuhiro Iwamatsu #define CONFIG_SH		1
316f0da497SNobuhiro Iwamatsu #define CONFIG_SH4		1
326f0da497SNobuhiro Iwamatsu #define CONFIG_CPU_SH7723	1
336f0da497SNobuhiro Iwamatsu #define CONFIG_AP325RXA	1
346f0da497SNobuhiro Iwamatsu 
356f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_LOADB
366f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_LOADS
376f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_FLASH
386f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_MEMORY
396f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_NET
406f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_PING
416f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_NFS
426f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_SDRAM
43bdab39d3SMike Frysinger #define CONFIG_CMD_SAVEENV
446f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_IDE
456f0da497SNobuhiro Iwamatsu #define CONFIG_CMD_EXT2
466f0da497SNobuhiro Iwamatsu #define CONFIG_DOS_PARTITION
476f0da497SNobuhiro Iwamatsu 
486f0da497SNobuhiro Iwamatsu #define CONFIG_BAUDRATE		38400
496f0da497SNobuhiro Iwamatsu #define CONFIG_BOOTDELAY	3
506f0da497SNobuhiro Iwamatsu #define CONFIG_BOOTARGS		"console=ttySC2,38400"
516f0da497SNobuhiro Iwamatsu 
526f0da497SNobuhiro Iwamatsu #define CONFIG_VERSION_VARIABLE
536f0da497SNobuhiro Iwamatsu #undef  CONFIG_SHOW_BOOT_PROGRESS
546f0da497SNobuhiro Iwamatsu 
556f0da497SNobuhiro Iwamatsu /* SMC9118 */
566f0da497SNobuhiro Iwamatsu #define CONFIG_DRIVER_SMC911X 1
576f0da497SNobuhiro Iwamatsu #define CONFIG_DRIVER_SMC911X_32_BIT 1
586f0da497SNobuhiro Iwamatsu #define CONFIG_DRIVER_SMC911X_BASE 0xB6080000
596f0da497SNobuhiro Iwamatsu 
606f0da497SNobuhiro Iwamatsu /* MEMORY */
616f0da497SNobuhiro Iwamatsu #define AP325RXA_SDRAM_BASE		(0x88000000)
626f0da497SNobuhiro Iwamatsu #define AP325RXA_FLASH_BASE_1		(0xA0000000)
636f0da497SNobuhiro Iwamatsu #define AP325RXA_FLASH_BANK_SIZE	(128 * 1024 * 1024)
646f0da497SNobuhiro Iwamatsu 
656f0da497SNobuhiro Iwamatsu /* undef to save memory	*/
666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP
676f0da497SNobuhiro Iwamatsu /* Monitor Command Prompt */
686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT		"=> "
696f0da497SNobuhiro Iwamatsu /* Buffer size for input from the Console */
706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE		256
716f0da497SNobuhiro Iwamatsu /* Buffer size for Console output */
726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE		256
736f0da497SNobuhiro Iwamatsu /* max args accepted for monitor commands */
746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS		16
756f0da497SNobuhiro Iwamatsu /* Buffer size for Boot Arguments passed to kernel */
766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE	512
776f0da497SNobuhiro Iwamatsu /* List of legal baudrate settings for this board */
786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE	{ 38400 }
796f0da497SNobuhiro Iwamatsu 
806f0da497SNobuhiro Iwamatsu /* SCIF */
816f0da497SNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE 1
826f0da497SNobuhiro Iwamatsu #define CONFIG_SCIF_A		1 /* SH7723 has SCIF and SCIFA */
836f0da497SNobuhiro Iwamatsu #define CONFIG_CONS_SCIF5	1
846f0da497SNobuhiro Iwamatsu 
856f0da497SNobuhiro Iwamatsu /* Suppress display of console information at boot */
866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_CONSOLE_INFO_QUIET
876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
896f0da497SNobuhiro Iwamatsu 
906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START	(AP325RXA_SDRAM_BASE)
916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
926f0da497SNobuhiro Iwamatsu 
936f0da497SNobuhiro Iwamatsu /* Enable alternate, more extensive, memory test */
946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_ALT_MEMTEST
956f0da497SNobuhiro Iwamatsu /* Scratch address used by the alternate memory test */
966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_MEMTEST_SCRATCH
976f0da497SNobuhiro Iwamatsu 
986f0da497SNobuhiro Iwamatsu /* Enable temporary baudrate change while serial download */
996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
1006f0da497SNobuhiro Iwamatsu 
1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE	(AP325RXA_SDRAM_BASE)
1026f0da497SNobuhiro Iwamatsu /* maybe more, but if so u-boot doesn't know about it... */
1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
1046f0da497SNobuhiro Iwamatsu /* default load address for scripts ?!? */
1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
1066f0da497SNobuhiro Iwamatsu 
1076f0da497SNobuhiro Iwamatsu /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE	(AP325RXA_FLASH_BASE_1)
1096f0da497SNobuhiro Iwamatsu /* Monitor size */
1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
1116f0da497SNobuhiro Iwamatsu /* Size of DRAM reserved for malloc() use */
1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
1136f0da497SNobuhiro Iwamatsu /* size in bytes reserved for initial data */
1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE	(256)
1156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
1166f0da497SNobuhiro Iwamatsu 
1176f0da497SNobuhiro Iwamatsu /* FLASH */
1186f0da497SNobuhiro Iwamatsu #define CONFIG_FLASH_CFI_DRIVER 1
1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI
1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_FLASH_QUIET_TEST
1216f0da497SNobuhiro Iwamatsu /* print 'E' for empty sector on flinfo */
1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO
1236f0da497SNobuhiro Iwamatsu /* Physical start address of Flash memory */
1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE	(AP325RXA_FLASH_BASE_1)
1256f0da497SNobuhiro Iwamatsu /* Max number of sectors on each Flash chip */
1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT	512
1276f0da497SNobuhiro Iwamatsu 
1286f0da497SNobuhiro Iwamatsu /*
1296f0da497SNobuhiro Iwamatsu  * IDE support
1306f0da497SNobuhiro Iwamatsu  */
1316f0da497SNobuhiro Iwamatsu #define CONFIG_IDE_RESET	1
1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIO_MODE		1
1336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE	1
1356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR	0xB4180000
1366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE		2	/* 1bit shift */
1376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET	0x200	/* data reg offset */
1386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET	0x200	/* reg offset */
1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET	0x210	/* alternate register offset */
1406f0da497SNobuhiro Iwamatsu 
1416f0da497SNobuhiro Iwamatsu /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS	1
1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
1446f0da497SNobuhiro Iwamatsu 
1456f0da497SNobuhiro Iwamatsu /* Timeout for Flash erase operations (in ms) */
1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
1476f0da497SNobuhiro Iwamatsu /* Timeout for Flash write operations (in ms) */
1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
1496f0da497SNobuhiro Iwamatsu /* Timeout for Flash set sector lock bit operations (in ms) */
1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
1516f0da497SNobuhiro Iwamatsu /* Timeout for Flash clear lock bit operations (in ms) */
1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
1536f0da497SNobuhiro Iwamatsu 
1546f0da497SNobuhiro Iwamatsu /*
1556f0da497SNobuhiro Iwamatsu  * Use hardware flash sectors protection instead
1566f0da497SNobuhiro Iwamatsu  * of U-Boot software protection
1576f0da497SNobuhiro Iwamatsu  */
1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_FLASH_PROTECTION
1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
1606f0da497SNobuhiro Iwamatsu 
1616f0da497SNobuhiro Iwamatsu /* ENV setting */
1625a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH
1636f0da497SNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE	1
1640e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
1650e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
1666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
1676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
1690e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
1706f0da497SNobuhiro Iwamatsu 
1716f0da497SNobuhiro Iwamatsu /* Board Clock */
1726f0da497SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ	33333333
1736f0da497SNobuhiro Iwamatsu #define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
174*8dd29c87SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ		1000
1756f0da497SNobuhiro Iwamatsu 
1766f0da497SNobuhiro Iwamatsu #endif	/* __AP325RXA_H */
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