1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26f0da497SNobuhiro Iwamatsu /* 36f0da497SNobuhiro Iwamatsu * Configuation settings for the Renesas Solutions AP-325RXA board 46f0da497SNobuhiro Iwamatsu * 56f0da497SNobuhiro Iwamatsu * Copyright (C) 2008 Renesas Solutions Corp. 66f0da497SNobuhiro Iwamatsu * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 76f0da497SNobuhiro Iwamatsu */ 86f0da497SNobuhiro Iwamatsu 96f0da497SNobuhiro Iwamatsu #ifndef __AP325RXA_H 106f0da497SNobuhiro Iwamatsu #define __AP325RXA_H 116f0da497SNobuhiro Iwamatsu 126f0da497SNobuhiro Iwamatsu #define CONFIG_CPU_SH7723 1 136f0da497SNobuhiro Iwamatsu 1418a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 156f0da497SNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 166f0da497SNobuhiro Iwamatsu 176f0da497SNobuhiro Iwamatsu /* MEMORY */ 186f0da497SNobuhiro Iwamatsu #define AP325RXA_SDRAM_BASE (0x88000000) 196f0da497SNobuhiro Iwamatsu #define AP325RXA_FLASH_BASE_1 (0xA0000000) 206f0da497SNobuhiro Iwamatsu #define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024) 216f0da497SNobuhiro Iwamatsu 226f0da497SNobuhiro Iwamatsu /* undef to save memory */ 236f0da497SNobuhiro Iwamatsu /* Monitor Command Prompt */ 246f0da497SNobuhiro Iwamatsu /* Buffer size for Console output */ 256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE 256 266f0da497SNobuhiro Iwamatsu /* List of legal baudrate settings for this board */ 276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE { 38400 } 286f0da497SNobuhiro Iwamatsu 296f0da497SNobuhiro Iwamatsu /* SCIF */ 306f0da497SNobuhiro Iwamatsu #define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */ 316f0da497SNobuhiro Iwamatsu #define CONFIG_CONS_SCIF5 1 326f0da497SNobuhiro Iwamatsu 336f0da497SNobuhiro Iwamatsu /* Suppress display of console information at boot */ 346f0da497SNobuhiro Iwamatsu 356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE) 366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 376f0da497SNobuhiro Iwamatsu 386f0da497SNobuhiro Iwamatsu /* Enable alternate, more extensive, memory test */ 396f0da497SNobuhiro Iwamatsu /* Scratch address used by the alternate memory test */ 406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_MEMTEST_SCRATCH 416f0da497SNobuhiro Iwamatsu 426f0da497SNobuhiro Iwamatsu /* Enable temporary baudrate change while serial download */ 436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_LOADS_BAUD_CHANGE 446f0da497SNobuhiro Iwamatsu 456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE) 466f0da497SNobuhiro Iwamatsu /* maybe more, but if so u-boot doesn't know about it... */ 476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 486f0da497SNobuhiro Iwamatsu /* default load address for scripts ?!? */ 496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 506f0da497SNobuhiro Iwamatsu 516f0da497SNobuhiro Iwamatsu /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1) 536f0da497SNobuhiro Iwamatsu /* Monitor size */ 546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 556f0da497SNobuhiro Iwamatsu /* Size of DRAM reserved for malloc() use */ 566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 586f0da497SNobuhiro Iwamatsu 596f0da497SNobuhiro Iwamatsu /* FLASH */ 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_QUIET_TEST 616f0da497SNobuhiro Iwamatsu /* print 'E' for empty sector on flinfo */ 626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 636f0da497SNobuhiro Iwamatsu /* Physical start address of Flash memory */ 646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1) 656f0da497SNobuhiro Iwamatsu /* Max number of sectors on each Flash chip */ 666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 512 676f0da497SNobuhiro Iwamatsu 686f0da497SNobuhiro Iwamatsu /* 696f0da497SNobuhiro Iwamatsu * IDE support 706f0da497SNobuhiro Iwamatsu */ 716f0da497SNobuhiro Iwamatsu #define CONFIG_IDE_RESET 1 726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIO_MODE 1 736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000 766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */ 786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */ 796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */ 80f2a37fcdSAlbert Aribaud #define CONFIG_IDE_SWAP_IO 816f0da497SNobuhiro Iwamatsu 826f0da497SNobuhiro Iwamatsu /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)} 856f0da497SNobuhiro Iwamatsu 866f0da497SNobuhiro Iwamatsu /* Timeout for Flash erase operations (in ms) */ 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 886f0da497SNobuhiro Iwamatsu /* Timeout for Flash write operations (in ms) */ 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 906f0da497SNobuhiro Iwamatsu /* Timeout for Flash set sector lock bit operations (in ms) */ 916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 926f0da497SNobuhiro Iwamatsu /* Timeout for Flash clear lock bit operations (in ms) */ 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 946f0da497SNobuhiro Iwamatsu 956f0da497SNobuhiro Iwamatsu /* 966f0da497SNobuhiro Iwamatsu * Use hardware flash sectors protection instead 976f0da497SNobuhiro Iwamatsu * of U-Boot software protection 986f0da497SNobuhiro Iwamatsu */ 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_DIRECT_FLASH_TFTP 1006f0da497SNobuhiro Iwamatsu 1016f0da497SNobuhiro Iwamatsu /* ENV setting */ 1026f0da497SNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE 1 1030e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE (128 * 1024) 1040e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 1080e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 1096f0da497SNobuhiro Iwamatsu 1106f0da497SNobuhiro Iwamatsu /* Board Clock */ 1116f0da497SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 33333333 112684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 1136f0da497SNobuhiro Iwamatsu 1146f0da497SNobuhiro Iwamatsu #endif /* __AP325RXA_H */ 115