1 /* 2 * Sysam AMCORE board configuration 3 * 4 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __AMCORE_CONFIG_H 10 #define __AMCORE_CONFIG_H 11 12 #define CONFIG_AMCORE 13 #define CONFIG_HOSTNAME AMCORE 14 15 #define CONFIG_MCFTMR 16 #define CONFIG_MCFUART 17 #define CONFIG_SYS_UART_PORT 0 18 #define CONFIG_BAUDRATE 115200 19 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 20 21 #define CONFIG_BOOTDELAY 1 22 #define CONFIG_BOOTCOMMAND "bootm ffc20000" 23 24 #undef CONFIG_CMD_AES 25 #define CONFIG_CMD_DIAG 26 27 /* undef to save memory */ 28 #undef CONFIG_SYS_LONGHELP 29 30 #if defined(CONFIG_CMD_KGDB) 31 /* Console I/O buff. size */ 32 #define CONFIG_SYS_CBSIZE 1024 33 #else 34 #define CONFIG_SYS_CBSIZE 256 35 #endif 36 /* Print buffer size */ 37 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 38 sizeof(CONFIG_SYS_PROMPT)+16) 39 /* max number of command args */ 40 #define CONFIG_SYS_MAXARGS 16 41 /* Boot argument buffer size */ 42 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 43 44 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */ 45 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 46 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 47 48 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ 49 50 #define CONFIG_SYS_MEMTEST_START 0x0 51 #define CONFIG_SYS_MEMTEST_END 0x1000000 52 53 #define CONFIG_SYS_HZ 1000 54 55 #define CONFIG_SYS_CLK 45000000 56 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) 57 /* Register Base Addrs */ 58 #define CONFIG_SYS_MBAR 0x10000000 59 /* Definitions for initial stack pointer and data area (in DPRAM) */ 60 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 61 /* size of internal SRAM */ 62 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 63 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 64 GENERATED_GBL_DATA_SIZE) 65 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 66 67 #define CONFIG_SYS_SDRAM_BASE 0x00000000 68 #define CONFIG_SYS_SDRAM_SIZE 0x1000000 69 #define CONFIG_SYS_FLASH_BASE 0xffc00000 70 #define CONFIG_SYS_MAX_FLASH_BANKS 1 71 #define CONFIG_SYS_MAX_FLASH_SECT 1024 72 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 73 74 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_FLASH_CFI_DRIVER 76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 77 /* amcore design has flash data bytes wired swapped */ 78 #define CONFIG_SYS_WRITE_SWAPPED_DATA 79 /* reserve 128-4KB */ 80 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 81 #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) 82 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 83 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 84 85 #define CONFIG_ENV_IS_IN_FLASH 1 86 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 87 CONFIG_SYS_MONITOR_LEN) 88 #define CONFIG_ENV_SIZE 0x1000 89 #define CONFIG_ENV_SECT_SIZE 0x1000 90 91 #define LDS_BOARD_TEXT \ 92 . = DEFINED(env_offset) ? env_offset : .; \ 93 common/env_embedded.o (.text*); 94 95 /* memory map space for linux boot data */ 96 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 97 98 /* 99 * Cache Configuration 100 * 101 * Special 8K version 3 core cache. 102 * This is a single unified instruction/data cache. 103 * sdram - single region - no masks 104 */ 105 #define CONFIG_SYS_CACHELINE_SIZE 16 106 107 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 108 CONFIG_SYS_INIT_RAM_SIZE - 8) 109 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 110 CONFIG_SYS_INIT_RAM_SIZE - 4) 111 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 112 #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ 113 CF_ACR_EN) 114 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ 115 CF_CACR_EC) 116 117 /* CS0 - AMD Flash, address 0xffc00000 */ 118 #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) 119 /* 4MB, AA=0,V=1 C/I BIT for errata */ 120 #define CONFIG_SYS_CS0_MASK 0x003f0001 121 /* WS=10, AA=1, PS=16bit (10) */ 122 #define CONFIG_SYS_CS0_CTRL 0x1980 123 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ 124 #define CONFIG_SYS_CS1_BASE 0x3000 125 #define CONFIG_SYS_CS1_MASK 0x00070001 126 #define CONFIG_SYS_CS1_CTRL 0x0100 127 128 #endif /* __AMCORE_CONFIG_H */ 129 130