1 /* 2 * Sysam AMCORE board configuration 3 * 4 * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __AMCORE_CONFIG_H 10 #define __AMCORE_CONFIG_H 11 12 #define CONFIG_AMCORE 13 #define CONFIG_HOSTNAME AMCORE 14 15 #define CONFIG_MCFTMR 16 #define CONFIG_MCFUART 17 #define CONFIG_SYS_UART_PORT 0 18 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 19 20 #define CONFIG_BOOTCOMMAND "bootm ffc20000" 21 #define CONFIG_EXTRA_ENV_SETTINGS \ 22 "upgrade_uboot=loady; " \ 23 "protect off 0xffc00000 0xffc1ffff; " \ 24 "erase 0xffc00000 0xffc1ffff; " \ 25 "cp.b 0x20000 0xffc00000 ${filesize}\0" \ 26 "upgrade_kernel=loady; " \ 27 "erase 0xffc20000 0xffefffff; " \ 28 "cp.b 0x20000 0xffc20000 ${filesize}\0" \ 29 "upgrade_jffs2=loady; " \ 30 "erase 0xfff00000 0xffffffff; " \ 31 "cp.b 0x20000 0xfff00000 ${filesize}\0" 32 33 /* undef to save memory */ 34 #undef CONFIG_SYS_LONGHELP 35 36 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 37 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 38 39 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ 40 41 #define CONFIG_SYS_MEMTEST_START 0x0 42 #define CONFIG_SYS_MEMTEST_END 0x1000000 43 44 #define CONFIG_SYS_HZ 1000 45 46 #define CONFIG_SYS_CLK 45000000 47 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) 48 /* Register Base Addrs */ 49 #define CONFIG_SYS_MBAR 0x10000000 50 /* Definitions for initial stack pointer and data area (in DPRAM) */ 51 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 52 /* size of internal SRAM */ 53 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 54 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 55 GENERATED_GBL_DATA_SIZE) 56 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 57 58 #define CONFIG_SYS_SDRAM_BASE 0x00000000 59 #define CONFIG_SYS_SDRAM_SIZE 0x1000000 60 #define CONFIG_SYS_FLASH_BASE 0xffc00000 61 #define CONFIG_SYS_MAX_FLASH_BANKS 1 62 #define CONFIG_SYS_MAX_FLASH_SECT 1024 63 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 64 65 #define CONFIG_SYS_FLASH_CFI 66 #define CONFIG_FLASH_CFI_DRIVER 67 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 68 /* amcore design has flash data bytes wired swapped */ 69 #define CONFIG_SYS_WRITE_SWAPPED_DATA 70 /* reserve 128-4KB */ 71 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 72 #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) 73 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 74 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 75 76 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 77 CONFIG_SYS_MONITOR_LEN) 78 #define CONFIG_ENV_SIZE 0x1000 79 #define CONFIG_ENV_SECT_SIZE 0x1000 80 81 #define LDS_BOARD_TEXT \ 82 . = DEFINED(env_offset) ? env_offset : .; \ 83 env/embedded.o(.text*); 84 85 /* memory map space for linux boot data */ 86 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 87 88 /* 89 * Cache Configuration 90 * 91 * Special 8K version 3 core cache. 92 * This is a single unified instruction/data cache. 93 * sdram - single region - no masks 94 */ 95 #define CONFIG_SYS_CACHELINE_SIZE 16 96 97 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 98 CONFIG_SYS_INIT_RAM_SIZE - 8) 99 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 100 CONFIG_SYS_INIT_RAM_SIZE - 4) 101 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 102 #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ 103 CF_ACR_EN) 104 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ 105 CF_CACR_EC) 106 107 /* CS0 - AMD Flash, address 0xffc00000 */ 108 #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) 109 /* 4MB, AA=0,V=1 C/I BIT for errata */ 110 #define CONFIG_SYS_CS0_MASK 0x003f0001 111 /* WS=10, AA=1, PS=16bit (10) */ 112 #define CONFIG_SYS_CS0_CTRL 0x1980 113 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ 114 #define CONFIG_SYS_CS1_BASE 0x3000 115 #define CONFIG_SYS_CS1_MASK 0x00070001 116 #define CONFIG_SYS_CS1_CTRL 0x0100 117 118 #endif /* __AMCORE_CONFIG_H */ 119 120