1 /* 2 * Sysam AMCORE board configuration 3 * 4 * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __AMCORE_CONFIG_H 10 #define __AMCORE_CONFIG_H 11 12 #define CONFIG_AMCORE 13 #define CONFIG_HOSTNAME AMCORE 14 15 #define CONFIG_MCFTMR 16 #define CONFIG_MCFUART 17 #define CONFIG_SYS_UART_PORT 0 18 #define CONFIG_BAUDRATE 115200 19 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 20 21 #define CONFIG_BOOTCOMMAND "bootm ffc20000" 22 #define CONFIG_EXTRA_ENV_SETTINGS \ 23 "upgrade_uboot=loady; " \ 24 "protect off 0xffc00000 0xffc1ffff; " \ 25 "erase 0xffc00000 0xffc1ffff; " \ 26 "cp.b 0x20000 0xffc00000 ${filesize}\0" \ 27 "upgrade_kernel=loady; " \ 28 "erase 0xffc20000 0xffefffff; " \ 29 "cp.b 0x20000 0xffc20000 ${filesize}\0" \ 30 "upgrade_jffs2=loady; " \ 31 "erase 0xfff00000 0xffffffff; " \ 32 "cp.b 0x20000 0xfff00000 ${filesize}\0" 33 34 #undef CONFIG_CMD_AES 35 #define CONFIG_CMD_DIAG 36 37 /* undef to save memory */ 38 #undef CONFIG_SYS_LONGHELP 39 40 #if defined(CONFIG_CMD_KGDB) 41 /* Console I/O buff. size */ 42 #define CONFIG_SYS_CBSIZE 1024 43 #else 44 #define CONFIG_SYS_CBSIZE 256 45 #endif 46 /* Print buffer size */ 47 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 48 sizeof(CONFIG_SYS_PROMPT)+16) 49 /* max number of command args */ 50 #define CONFIG_SYS_MAXARGS 16 51 /* Boot argument buffer size */ 52 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 53 54 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */ 55 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 56 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 57 58 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ 59 60 #define CONFIG_SYS_MEMTEST_START 0x0 61 #define CONFIG_SYS_MEMTEST_END 0x1000000 62 63 #define CONFIG_SYS_HZ 1000 64 65 #define CONFIG_SYS_CLK 45000000 66 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) 67 /* Register Base Addrs */ 68 #define CONFIG_SYS_MBAR 0x10000000 69 /* Definitions for initial stack pointer and data area (in DPRAM) */ 70 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 71 /* size of internal SRAM */ 72 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 73 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 74 GENERATED_GBL_DATA_SIZE) 75 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 76 77 #define CONFIG_SYS_SDRAM_BASE 0x00000000 78 #define CONFIG_SYS_SDRAM_SIZE 0x1000000 79 #define CONFIG_SYS_FLASH_BASE 0xffc00000 80 #define CONFIG_SYS_MAX_FLASH_BANKS 1 81 #define CONFIG_SYS_MAX_FLASH_SECT 1024 82 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 83 84 #define CONFIG_SYS_FLASH_CFI 85 #define CONFIG_FLASH_CFI_DRIVER 86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 87 /* amcore design has flash data bytes wired swapped */ 88 #define CONFIG_SYS_WRITE_SWAPPED_DATA 89 /* reserve 128-4KB */ 90 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 91 #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) 92 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 93 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 94 95 #define CONFIG_ENV_IS_IN_FLASH 1 96 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 97 CONFIG_SYS_MONITOR_LEN) 98 #define CONFIG_ENV_SIZE 0x1000 99 #define CONFIG_ENV_SECT_SIZE 0x1000 100 101 #define LDS_BOARD_TEXT \ 102 . = DEFINED(env_offset) ? env_offset : .; \ 103 common/env_embedded.o (.text*); 104 105 /* memory map space for linux boot data */ 106 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 107 108 /* 109 * Cache Configuration 110 * 111 * Special 8K version 3 core cache. 112 * This is a single unified instruction/data cache. 113 * sdram - single region - no masks 114 */ 115 #define CONFIG_SYS_CACHELINE_SIZE 16 116 117 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 118 CONFIG_SYS_INIT_RAM_SIZE - 8) 119 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 120 CONFIG_SYS_INIT_RAM_SIZE - 4) 121 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 122 #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ 123 CF_ACR_EN) 124 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ 125 CF_CACR_EC) 126 127 /* CS0 - AMD Flash, address 0xffc00000 */ 128 #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) 129 /* 4MB, AA=0,V=1 C/I BIT for errata */ 130 #define CONFIG_SYS_CS0_MASK 0x003f0001 131 /* WS=10, AA=1, PS=16bit (10) */ 132 #define CONFIG_SYS_CS0_CTRL 0x1980 133 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ 134 #define CONFIG_SYS_CS1_BASE 0x3000 135 #define CONFIG_SYS_CS1_MASK 0x00070001 136 #define CONFIG_SYS_CS1_CTRL 0x0100 137 138 #endif /* __AMCORE_CONFIG_H */ 139 140