1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Sysam AMCORE board configuration 4 * 5 * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it> 6 */ 7 8 #ifndef __AMCORE_CONFIG_H 9 #define __AMCORE_CONFIG_H 10 11 #define CONFIG_HOSTNAME "AMCORE" 12 13 #define CONFIG_MCFTMR 14 #define CONFIG_MCFUART 15 #define CONFIG_SYS_UART_PORT 0 16 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 17 18 #define CONFIG_BOOTCOMMAND "bootm ffc20000" 19 #define CONFIG_EXTRA_ENV_SETTINGS \ 20 "upgrade_uboot=loady; " \ 21 "protect off 0xffc00000 0xffc1ffff; " \ 22 "erase 0xffc00000 0xffc1ffff; " \ 23 "cp.b 0x20000 0xffc00000 ${filesize}\0" \ 24 "upgrade_kernel=loady; " \ 25 "erase 0xffc20000 0xffefffff; " \ 26 "cp.b 0x20000 0xffc20000 ${filesize}\0" \ 27 "upgrade_jffs2=loady; " \ 28 "erase 0xfff00000 0xffffffff; " \ 29 "cp.b 0x20000 0xfff00000 ${filesize}\0" 30 31 /* undef to save memory */ 32 33 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 34 35 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ 36 37 #define CONFIG_SYS_MEMTEST_START 0x0 38 #define CONFIG_SYS_MEMTEST_END 0x1000000 39 40 #define CONFIG_SYS_HZ 1000 41 42 #define CONFIG_SYS_CLK 45000000 43 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) 44 /* Register Base Addrs */ 45 #define CONFIG_SYS_MBAR 0x10000000 46 /* Definitions for initial stack pointer and data area (in DPRAM) */ 47 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 48 /* size of internal SRAM */ 49 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 50 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 51 GENERATED_GBL_DATA_SIZE) 52 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 53 54 #define CONFIG_SYS_SDRAM_BASE 0x00000000 55 #define CONFIG_SYS_SDRAM_SIZE 0x1000000 56 #define CONFIG_SYS_FLASH_BASE 0xffc00000 57 #define CONFIG_SYS_MAX_FLASH_BANKS 1 58 #define CONFIG_SYS_MAX_FLASH_SECT 1024 59 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 60 61 #define CONFIG_SYS_FLASH_CFI 62 #define CONFIG_FLASH_CFI_DRIVER 63 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 64 /* amcore design has flash data bytes wired swapped */ 65 #define CONFIG_SYS_WRITE_SWAPPED_DATA 66 /* reserve 128-4KB */ 67 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 68 #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) 69 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 70 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 71 72 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 73 CONFIG_SYS_MONITOR_LEN) 74 #define CONFIG_ENV_SIZE 0x1000 75 #define CONFIG_ENV_SECT_SIZE 0x1000 76 77 #define LDS_BOARD_TEXT \ 78 . = DEFINED(env_offset) ? env_offset : .; \ 79 env/embedded.o(.text*); 80 81 /* memory map space for linux boot data */ 82 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 83 84 /* 85 * Cache Configuration 86 * 87 * Special 8K version 3 core cache. 88 * This is a single unified instruction/data cache. 89 * sdram - single region - no masks 90 */ 91 #define CONFIG_SYS_CACHELINE_SIZE 16 92 93 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 94 CONFIG_SYS_INIT_RAM_SIZE - 8) 95 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 96 CONFIG_SYS_INIT_RAM_SIZE - 4) 97 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 98 #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ 99 CF_ACR_EN) 100 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ 101 CF_CACR_EC) 102 103 /* CS0 - AMD Flash, address 0xffc00000 */ 104 #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) 105 /* 4MB, AA=0,V=1 C/I BIT for errata */ 106 #define CONFIG_SYS_CS0_MASK 0x003f0001 107 /* WS=10, AA=1, PS=16bit (10) */ 108 #define CONFIG_SYS_CS0_CTRL 0x1980 109 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ 110 #define CONFIG_SYS_CS1_BASE 0x3000 111 #define CONFIG_SYS_CS1_MASK 0x00070001 112 #define CONFIG_SYS_CS1_CTRL 0x0100 113 114 #endif /* __AMCORE_CONFIG_H */ 115 116