xref: /openbmc/u-boot/include/configs/amcore.h (revision 699e831e)
1 /*
2  * Sysam AMCORE board configuration
3  *
4  * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8 
9 #ifndef __AMCORE_CONFIG_H
10 #define __AMCORE_CONFIG_H
11 
12 #define CONFIG_HOSTNAME			"AMCORE"
13 
14 #define CONFIG_MCFTMR
15 #define CONFIG_MCFUART
16 #define CONFIG_SYS_UART_PORT		0
17 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
18 
19 #define CONFIG_BOOTCOMMAND		"bootm ffc20000"
20 #define CONFIG_EXTRA_ENV_SETTINGS				\
21 	"upgrade_uboot=loady; "					\
22 		"protect off 0xffc00000 0xffc1ffff; "		\
23 		"erase 0xffc00000 0xffc1ffff; "			\
24 		"cp.b 0x20000 0xffc00000 ${filesize}\0"		\
25 	"upgrade_kernel=loady; "				\
26 		"erase 0xffc20000 0xffefffff; "			\
27 		"cp.b 0x20000 0xffc20000 ${filesize}\0"		\
28 	"upgrade_jffs2=loady; "					\
29 		"erase 0xfff00000 0xffffffff; "			\
30 		"cp.b 0x20000 0xfff00000 ${filesize}\0"
31 
32 /* undef to save memory	*/
33 
34 #define CONFIG_MX_CYCLIC		1 /* enable mdc/mwc commands	*/
35 
36 #define CONFIG_SYS_LOAD_ADDR		0x20000	/* default load address */
37 
38 #define CONFIG_SYS_MEMTEST_START	0x0
39 #define CONFIG_SYS_MEMTEST_END		0x1000000
40 
41 #define CONFIG_SYS_HZ			1000
42 
43 #define CONFIG_SYS_CLK			45000000
44 #define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 2)
45 /* Register Base Addrs */
46 #define CONFIG_SYS_MBAR			0x10000000
47 /* Definitions for initial stack pointer and data area (in DPRAM) */
48 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
49 /* size of internal SRAM */
50 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000
51 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
52 					 GENERATED_GBL_DATA_SIZE)
53 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
54 
55 #define CONFIG_SYS_SDRAM_BASE		0x00000000
56 #define CONFIG_SYS_SDRAM_SIZE		0x1000000
57 #define CONFIG_SYS_FLASH_BASE		0xffc00000
58 #define CONFIG_SYS_MAX_FLASH_BANKS	1
59 #define CONFIG_SYS_MAX_FLASH_SECT	1024
60 #define CONFIG_SYS_FLASH_ERASE_TOUT	1000
61 
62 #define CONFIG_SYS_FLASH_CFI
63 #define CONFIG_FLASH_CFI_DRIVER
64 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
65 /* amcore design has flash data bytes wired swapped */
66 #define CONFIG_SYS_WRITE_SWAPPED_DATA
67 /* reserve 128-4KB */
68 #define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
69 #define CONFIG_SYS_MONITOR_LEN          ((128 - 4) * 1024)
70 #define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
71 #define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
72 
73 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
74 					 CONFIG_SYS_MONITOR_LEN)
75 #define CONFIG_ENV_SIZE			0x1000
76 #define CONFIG_ENV_SECT_SIZE		0x1000
77 
78 #define LDS_BOARD_TEXT \
79 	. = DEFINED(env_offset) ? env_offset : .; \
80 	env/embedded.o(.text*);
81 
82 /* memory map space for linux boot data */
83 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
84 
85 /*
86  * Cache Configuration
87  *
88  * Special 8K version 3 core cache.
89  * This is a single unified instruction/data cache.
90  * sdram - single region - no masks
91  */
92 #define CONFIG_SYS_CACHELINE_SIZE	16
93 
94 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
95 					 CONFIG_SYS_INIT_RAM_SIZE - 8)
96 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
97 					 CONFIG_SYS_INIT_RAM_SIZE - 4)
98 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
99 #define CONFIG_SYS_CACHE_ACR0		(CF_ACR_CM_WT | CF_ACR_SM_ALL | \
100 					 CF_ACR_EN)
101 #define CONFIG_SYS_CACHE_ICACR		(CF_CACR_DCM_P | CF_CACR_ESB | \
102 					 CF_CACR_EC)
103 
104 /* CS0 - AMD Flash, address 0xffc00000 */
105 #define	CONFIG_SYS_CS0_BASE		(CONFIG_SYS_FLASH_BASE>>16)
106 /* 4MB, AA=0,V=1  C/I BIT for errata */
107 #define	CONFIG_SYS_CS0_MASK		0x003f0001
108 /* WS=10, AA=1, PS=16bit (10) */
109 #define	CONFIG_SYS_CS0_CTRL		0x1980
110 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
111 #define CONFIG_SYS_CS1_BASE		0x3000
112 #define CONFIG_SYS_CS1_MASK		0x00070001
113 #define CONFIG_SYS_CS1_CTRL		0x0100
114 
115 #endif  /* __AMCORE_CONFIG_H */
116 
117