1 /* 2 * Sysam AMCORE board configuration 3 * 4 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __AMCORE_CONFIG_H 10 #define __AMCORE_CONFIG_H 11 12 #define CONFIG_AMCORE 13 #define CONFIG_HOSTNAME AMCORE 14 15 #define CONFIG_MCFTMR 16 #define CONFIG_MCFUART 17 #define CONFIG_SYS_UART_PORT 0 18 #define CONFIG_BAUDRATE 115200 19 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 20 21 #define CONFIG_BOOTDELAY 1 22 #define CONFIG_BOOTCOMMAND "bootm ffc20000" 23 24 #include <config_cmd_default.h> 25 #undef CONFIG_CMD_AES 26 #undef CONFIG_CMD_BOOTD 27 #undef CONFIG_CMD_NET 28 #undef CONFIG_CMD_NFS 29 #undef CONFIG_CMD_FPGA 30 #undef CONFIG_CMD_XIMG 31 #define CONFIG_CMD_CACHE 32 #define CONFIG_CMD_TIMER 33 #define CONFIG_CMD_DIAG 34 35 #define CONFIG_SYS_PROMPT "amcore $ " 36 /* undef to save memory */ 37 #undef CONFIG_SYS_LONGHELP 38 39 #if defined(CONFIG_CMD_KGDB) 40 /* Console I/O buff. size */ 41 #define CONFIG_SYS_CBSIZE 1024 42 #else 43 #define CONFIG_SYS_CBSIZE 256 44 #endif 45 /* Print buffer size */ 46 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 47 sizeof(CONFIG_SYS_PROMPT)+16) 48 /* max number of command args */ 49 #define CONFIG_SYS_MAXARGS 16 50 /* Boot argument buffer size */ 51 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 52 53 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */ 54 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 55 #define CONFIG_LOOPW 1 /* enable loopw command */ 56 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 57 58 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ 59 60 #define CONFIG_SYS_MEMTEST_START 0x0 61 #define CONFIG_SYS_MEMTEST_END 0x1000000 62 63 #define CONFIG_SYS_HZ 1000 64 65 #define CONFIG_SYS_CLK 45000000 66 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) 67 /* Register Base Addrs */ 68 #define CONFIG_SYS_MBAR 0x10000000 69 /* Definitions for initial stack pointer and data area (in DPRAM) */ 70 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 71 /* size of internal SRAM */ 72 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 73 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 74 GENERATED_GBL_DATA_SIZE) 75 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 76 77 #define CONFIG_SYS_SDRAM_BASE 0x00000000 78 #define CONFIG_SYS_SDRAM_SIZE 0x1000000 79 #define CONFIG_SYS_FLASH_BASE 0xffc00000 80 #define CONFIG_SYS_MAX_FLASH_BANKS 1 81 #define CONFIG_SYS_MAX_FLASH_SECT 1024 82 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 83 84 #define CONFIG_SYS_FLASH_CFI 85 #define CONFIG_FLASH_CFI_DRIVER 86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 87 /* amcore design has flash data bytes wired swapped */ 88 #define CONFIG_SYS_WRITE_SWAPPED_DATA 89 /* reserve 128-4KB */ 90 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 91 #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) 92 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 93 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 94 95 #define CONFIG_ENV_IS_IN_FLASH 1 96 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 97 CONFIG_SYS_MONITOR_LEN) 98 #define CONFIG_ENV_SIZE 0x1000 99 #define CONFIG_ENV_SECT_SIZE 0x1000 100 101 /* memory map space for linux boot data */ 102 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 103 104 /* 105 * Cache Configuration 106 * 107 * Special 8K version 3 core cache. 108 * This is a single unified instruction/data cache. 109 * sdram - single region - no masks 110 */ 111 #define CONFIG_SYS_CACHELINE_SIZE 16 112 113 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 114 CONFIG_SYS_INIT_RAM_SIZE - 8) 115 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 116 CONFIG_SYS_INIT_RAM_SIZE - 4) 117 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 118 #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ 119 CF_ACR_EN) 120 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ 121 CF_CACR_EC) 122 123 /* CS0 - AMD Flash, address 0xffc00000 */ 124 #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) 125 /* 4MB, AA=0,V=1 C/I BIT for errata */ 126 #define CONFIG_SYS_CS0_MASK 0x003f0001 127 /* WS=10, AA=1, PS=16bit (10) */ 128 #define CONFIG_SYS_CS0_CTRL 0x1980 129 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ 130 #define CONFIG_SYS_CS1_BASE 0x3000 131 #define CONFIG_SYS_CS1_MASK 0x00070001 132 #define CONFIG_SYS_CS1_CTRL 0x0100 133 134 #endif /* __AMCORE_CONFIG_H */ 135 136