1 /* 2 * am3517_evm.h - Default configuration for AM3517 EVM board. 3 * 4 * Author: Vaibhav Hiremath <hvaibhav@ti.com> 5 * 6 * Based on omap3_evm_config.h 7 * 8 * Copyright (C) 2010 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 32 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 33 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ 34 35 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 36 37 #include <asm/arch/cpu.h> /* get chip and board defs */ 38 #include <asm/arch/omap3.h> 39 40 /* 41 * Display CPU and Board information 42 */ 43 #define CONFIG_DISPLAY_CPUINFO 1 44 #define CONFIG_DISPLAY_BOARDINFO 1 45 46 /* Clock Defines */ 47 #define V_OSCK 26000000 /* Clock output from T2 */ 48 #define V_SCLK (V_OSCK >> 1) 49 50 #undef CONFIG_USE_IRQ /* no support for IRQs */ 51 #define CONFIG_MISC_INIT_R 52 53 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 54 #define CONFIG_SETUP_MEMORY_TAGS 1 55 #define CONFIG_INITRD_TAG 1 56 #define CONFIG_REVISION_TAG 1 57 58 /* 59 * Size of malloc() pool 60 */ 61 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 63 /* 64 * DDR related 65 */ 66 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 67 68 /* 69 * Hardware drivers 70 */ 71 72 /* 73 * NS16550 Configuration 74 */ 75 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 76 77 #define CONFIG_SYS_NS16550 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 80 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 81 82 /* 83 * select serial console configuration 84 */ 85 #define CONFIG_CONS_INDEX 3 86 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 87 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ 88 89 /* allow to overwrite serial and ethaddr */ 90 #define CONFIG_ENV_OVERWRITE 91 #define CONFIG_BAUDRATE 115200 92 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 93 115200} 94 #define CONFIG_MMC 1 95 #define CONFIG_GENERIC_MMC 1 96 #define CONFIG_OMAP_HSMMC 1 97 #define CONFIG_DOS_PARTITION 1 98 99 /* 100 * USB configuration 101 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 102 * Enable CONFIG_MUSB_UDC for Device functionalities. 103 */ 104 #define CONFIG_USB_AM35X 1 105 #define CONFIG_MUSB_HCD 1 106 107 #ifdef CONFIG_USB_AM35X 108 109 #ifdef CONFIG_MUSB_HCD 110 #define CONFIG_CMD_USB 111 112 #define CONFIG_USB_STORAGE 113 #define CONGIG_CMD_STORAGE 114 #define CONFIG_CMD_FAT 115 116 #ifdef CONFIG_USB_KEYBOARD 117 #define CONFIG_SYS_USB_EVENT_POLL 118 #define CONFIG_PREBOOT "usb start" 119 #endif /* CONFIG_USB_KEYBOARD */ 120 121 #endif /* CONFIG_MUSB_HCD */ 122 123 #ifdef CONFIG_MUSB_UDC 124 /* USB device configuration */ 125 #define CONFIG_USB_DEVICE 1 126 #define CONFIG_USB_TTY 1 127 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 128 /* Change these to suit your needs */ 129 #define CONFIG_USBD_VENDORID 0x0451 130 #define CONFIG_USBD_PRODUCTID 0x5678 131 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 132 #define CONFIG_USBD_PRODUCT_NAME "AM3517EVM" 133 #endif /* CONFIG_MUSB_UDC */ 134 135 #endif /* CONFIG_USB_AM35X */ 136 137 /* commands to include */ 138 #include <config_cmd_default.h> 139 140 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 141 #define CONFIG_CMD_FAT /* FAT support */ 142 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 143 144 #define CONFIG_CMD_I2C /* I2C serial bus support */ 145 #define CONFIG_CMD_MMC /* MMC support */ 146 #define CONFIG_CMD_NAND /* NAND support */ 147 #define CONFIG_CMD_DHCP 148 #define CONFIG_CMD_PING 149 150 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 151 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 152 #undef CONFIG_CMD_IMI /* iminfo */ 153 #undef CONFIG_CMD_IMLS /* List all found images */ 154 155 #define CONFIG_SYS_NO_FLASH 156 #define CONFIG_HARD_I2C 1 157 #define CONFIG_SYS_I2C_SPEED 100000 158 #define CONFIG_SYS_I2C_SLAVE 1 159 #define CONFIG_SYS_I2C_BUS 0 160 #define CONFIG_SYS_I2C_BUS_SELECT 1 161 #define CONFIG_DRIVER_OMAP34XX_I2C 1 162 163 #undef CONFIG_CMD_NET 164 #undef CONFIG_CMD_NFS 165 /* 166 * Board NAND Info. 167 */ 168 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 169 /* to access nand */ 170 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 171 /* to access */ 172 /* nand at CS0 */ 173 174 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 175 /* NAND devices */ 176 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 177 178 #define CONFIG_JFFS2_NAND 179 /* nand device jffs2 lives on */ 180 #define CONFIG_JFFS2_DEV "nand0" 181 /* start of jffs2 partition */ 182 #define CONFIG_JFFS2_PART_OFFSET 0x680000 183 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 184 185 /* Environment information */ 186 #define CONFIG_BOOTDELAY 10 187 188 #define CONFIG_BOOTFILE "uImage" 189 190 #define CONFIG_EXTRA_ENV_SETTINGS \ 191 "loadaddr=0x82000000\0" \ 192 "console=ttyO2,115200n8\0" \ 193 "mmcdev=0\0" \ 194 "mmcargs=setenv bootargs console=${console} " \ 195 "root=/dev/mmcblk0p2 rw " \ 196 "rootfstype=ext3 rootwait\0" \ 197 "nandargs=setenv bootargs console=${console} " \ 198 "root=/dev/mtdblock4 rw " \ 199 "rootfstype=jffs2\0" \ 200 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 201 "bootscript=echo Running bootscript from mmc ...; " \ 202 "source ${loadaddr}\0" \ 203 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 204 "mmcboot=echo Booting from mmc ...; " \ 205 "run mmcargs; " \ 206 "bootm ${loadaddr}\0" \ 207 "nandboot=echo Booting from nand ...; " \ 208 "run nandargs; " \ 209 "nand read ${loadaddr} 280000 400000; " \ 210 "bootm ${loadaddr}\0" \ 211 212 #define CONFIG_BOOTCOMMAND \ 213 "if mmc rescan ${mmcdev}; then " \ 214 "if run loadbootscript; then " \ 215 "run bootscript; " \ 216 "else " \ 217 "if run loaduimage; then " \ 218 "run mmcboot; " \ 219 "else run nandboot; " \ 220 "fi; " \ 221 "fi; " \ 222 "else run nandboot; fi" 223 224 #define CONFIG_AUTO_COMPLETE 1 225 /* 226 * Miscellaneous configurable options 227 */ 228 #define V_PROMPT "AM3517_EVM # " 229 230 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 231 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 232 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 233 #define CONFIG_SYS_PROMPT V_PROMPT 234 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 235 /* Print Buffer Size */ 236 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 237 sizeof(CONFIG_SYS_PROMPT) + 16) 238 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 239 /* args */ 240 /* Boot Argument Buffer Size */ 241 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 242 /* memtest works on */ 243 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 244 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 245 0x01F00000) /* 31MB */ 246 247 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 248 /* address */ 249 250 /* 251 * AM3517 has 12 GP timers, they can be driven by the system clock 252 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 253 * This rate is divided by a local divisor. 254 */ 255 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 256 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 257 #define CONFIG_SYS_HZ 1000 258 259 /*----------------------------------------------------------------------- 260 * Stack sizes 261 * 262 * The stack sizes are set up in start.S using the settings below 263 */ 264 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 265 266 /*----------------------------------------------------------------------- 267 * Physical Memory Map 268 */ 269 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 270 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 271 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 272 273 /*----------------------------------------------------------------------- 274 * FLASH and environment organization 275 */ 276 277 /* **** PISMO SUPPORT *** */ 278 279 /* Configure the PISMO */ 280 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 281 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 282 283 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 284 /* on one chip */ 285 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 286 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 287 288 #if defined(CONFIG_CMD_NAND) 289 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 290 #endif 291 292 /* Monitor at start of flash */ 293 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 294 295 #define CONFIG_NAND_OMAP_GPMC 296 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 297 #define CONFIG_ENV_IS_IN_NAND 1 298 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 299 300 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 301 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 302 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 303 304 /*----------------------------------------------------------------------- 305 * CFI FLASH driver setup 306 */ 307 /* timeout values are in ticks */ 308 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 309 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 310 311 /* Flash banks JFFS2 should use */ 312 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 313 CONFIG_SYS_MAX_NAND_DEVICE) 314 #define CONFIG_SYS_JFFS2_MEM_NAND 315 /* use flash_info[2] */ 316 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 317 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 318 319 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 320 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 321 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 322 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 323 CONFIG_SYS_INIT_RAM_SIZE - \ 324 GENERATED_GBL_DATA_SIZE) 325 326 /* Defines for SPL */ 327 #define CONFIG_SPL 328 #define CONFIG_SPL_NAND_SIMPLE 329 #define CONFIG_SPL_TEXT_BASE 0x40200800 330 #define CONFIG_SPL_MAX_SIZE (45 * 1024) 331 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 332 333 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 334 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 335 336 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 337 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 338 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 339 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 340 341 #define CONFIG_SPL_LIBCOMMON_SUPPORT 342 #define CONFIG_SPL_LIBDISK_SUPPORT 343 #define CONFIG_SPL_I2C_SUPPORT 344 #define CONFIG_SPL_LIBGENERIC_SUPPORT 345 #define CONFIG_SPL_MMC_SUPPORT 346 #define CONFIG_SPL_FAT_SUPPORT 347 #define CONFIG_SPL_SERIAL_SUPPORT 348 #define CONFIG_SPL_NAND_SUPPORT 349 #define CONFIG_SPL_POWER_SUPPORT 350 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 351 352 /* NAND boot config */ 353 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 354 #define CONFIG_SYS_NAND_PAGE_COUNT 64 355 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 356 #define CONFIG_SYS_NAND_OOBSIZE 64 357 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 358 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 359 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 360 10, 11, 12, 13} 361 #define CONFIG_SYS_NAND_ECCSIZE 512 362 #define CONFIG_SYS_NAND_ECCBYTES 3 363 #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ 364 CONFIG_SYS_NAND_ECCSIZE) 365 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ 366 CONFIG_SYS_NAND_ECCSTEPS) 367 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 368 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 369 370 /* 371 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 372 * 64 bytes before this address should be set aside for u-boot.img's 373 * header. That is 0x800FFFC0--0x80100000 should not be used for any 374 * other needs. 375 */ 376 #define CONFIG_SYS_TEXT_BASE 0x80100000 377 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 378 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 379 380 #endif /* __CONFIG_H */ 381