1 /* 2 * am3517_evm.h - Default configuration for AM3517 EVM board. 3 * 4 * Author: Vaibhav Hiremath <hvaibhav@ti.com> 5 * 6 * Based on omap3_evm_config.h 7 * 8 * Copyright (C) 2010 Texas Instruments Incorporated 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ 21 #define CONFIG_OMAP_COMMON 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 28 29 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/omap.h> 31 32 /* 33 * Display CPU and Board information 34 */ 35 #define CONFIG_DISPLAY_CPUINFO 1 36 #define CONFIG_DISPLAY_BOARDINFO 1 37 38 /* Clock Defines */ 39 #define V_OSCK 26000000 /* Clock output from T2 */ 40 #define V_SCLK (V_OSCK >> 1) 41 42 #define CONFIG_MISC_INIT_R 43 44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 45 #define CONFIG_SETUP_MEMORY_TAGS 1 46 #define CONFIG_INITRD_TAG 1 47 #define CONFIG_REVISION_TAG 1 48 49 /* 50 * Size of malloc() pool 51 */ 52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 53 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 54 /* 55 * DDR related 56 */ 57 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 58 59 /* 60 * Hardware drivers 61 */ 62 63 /* 64 * OMAP GPIO configuration 65 */ 66 #define CONFIG_OMAP_GPIO 67 68 /* 69 * NS16550 Configuration 70 */ 71 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 72 73 #define CONFIG_SYS_NS16550 74 #define CONFIG_SYS_NS16550_SERIAL 75 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 76 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 77 78 /* 79 * select serial console configuration 80 */ 81 #define CONFIG_CONS_INDEX 3 82 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 83 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ 84 85 /* allow to overwrite serial and ethaddr */ 86 #define CONFIG_ENV_OVERWRITE 87 #define CONFIG_BAUDRATE 115200 88 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 89 115200} 90 #define CONFIG_MMC 1 91 #define CONFIG_GENERIC_MMC 1 92 #define CONFIG_OMAP_HSMMC 1 93 #define CONFIG_DOS_PARTITION 1 94 95 /* 96 * USB configuration 97 * Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard 98 * Enable CONFIG_MUSB_GADGET for Device functionalities. 99 */ 100 #define CONFIG_USB_MUSB_AM35X 101 #define CONFIG_MUSB_HOST 102 #define CONFIG_MUSB_PIO_ONLY 103 104 #ifdef CONFIG_USB_MUSB_AM35X 105 106 #ifdef CONFIG_MUSB_HOST 107 #define CONFIG_CMD_USB 108 109 #define CONFIG_USB_STORAGE 110 #define CONGIG_CMD_STORAGE 111 #define CONFIG_CMD_FAT 112 113 #ifdef CONFIG_USB_KEYBOARD 114 #define CONFIG_SYS_USB_EVENT_POLL 115 #define CONFIG_PREBOOT "usb start" 116 #endif /* CONFIG_USB_KEYBOARD */ 117 118 #endif /* CONFIG_MUSB_HOST */ 119 120 #ifdef CONFIG_MUSB_GADGET 121 #define CONFIG_USB_GADGET_DUALSPEED 122 #define CONFIG_USB_ETHER 123 #define CONFIG_USB_ETH_RNDIS 124 #endif /* CONFIG_MUSB_GADGET */ 125 126 #endif /* CONFIG_USB_MUSB_AM35X */ 127 128 /* commands to include */ 129 #include <config_cmd_default.h> 130 131 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 132 #define CONFIG_CMD_FAT /* FAT support */ 133 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 134 135 #define CONFIG_CMD_I2C /* I2C serial bus support */ 136 #define CONFIG_CMD_MMC /* MMC support */ 137 #define CONFIG_CMD_NAND /* NAND support */ 138 #define CONFIG_CMD_DHCP 139 #undef CONFIG_CMD_PING 140 141 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 142 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 143 #undef CONFIG_CMD_IMI /* iminfo */ 144 #undef CONFIG_CMD_IMLS /* List all found images */ 145 146 #define CONFIG_SYS_NO_FLASH 147 #define CONFIG_SYS_I2C 148 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 149 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 150 #define CONFIG_SYS_I2C_OMAP34XX 151 152 /* 153 * Ethernet 154 */ 155 #define CONFIG_DRIVER_TI_EMAC 156 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 157 #define CONFIG_MII 158 #define CONFIG_BOOTP_DEFAULT 159 #define CONFIG_BOOTP_DNS 160 #define CONFIG_BOOTP_DNS2 161 #define CONFIG_BOOTP_SEND_HOSTNAME 162 #define CONFIG_NET_RETRY_COUNT 10 163 164 /* 165 * Board NAND Info. 166 */ 167 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 168 /* to access nand */ 169 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 170 /* to access */ 171 /* nand at CS0 */ 172 173 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 174 /* NAND devices */ 175 #define CONFIG_JFFS2_NAND 176 /* nand device jffs2 lives on */ 177 #define CONFIG_JFFS2_DEV "nand0" 178 /* start of jffs2 partition */ 179 #define CONFIG_JFFS2_PART_OFFSET 0x680000 180 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 181 182 /* Environment information */ 183 #define CONFIG_BOOTDELAY 10 184 185 #define CONFIG_BOOTFILE "uImage" 186 187 #define CONFIG_EXTRA_ENV_SETTINGS \ 188 "loadaddr=0x82000000\0" \ 189 "console=ttyO2,115200n8\0" \ 190 "mmcdev=0\0" \ 191 "mmcargs=setenv bootargs console=${console} " \ 192 "root=/dev/mmcblk0p2 rw rootwait\0" \ 193 "nandargs=setenv bootargs console=${console} " \ 194 "root=/dev/mtdblock4 rw " \ 195 "rootfstype=jffs2\0" \ 196 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 197 "bootscript=echo Running bootscript from mmc ...; " \ 198 "source ${loadaddr}\0" \ 199 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 200 "mmcboot=echo Booting from mmc ...; " \ 201 "run mmcargs; " \ 202 "bootm ${loadaddr}\0" \ 203 "nandboot=echo Booting from nand ...; " \ 204 "run nandargs; " \ 205 "nand read ${loadaddr} 280000 400000; " \ 206 "bootm ${loadaddr}\0" \ 207 208 #define CONFIG_BOOTCOMMAND \ 209 "mmc dev ${mmcdev}; if mmc rescan; then " \ 210 "if run loadbootscript; then " \ 211 "run bootscript; " \ 212 "else " \ 213 "if run loaduimage; then " \ 214 "run mmcboot; " \ 215 "else run nandboot; " \ 216 "fi; " \ 217 "fi; " \ 218 "else run nandboot; fi" 219 220 #define CONFIG_AUTO_COMPLETE 1 221 /* 222 * Miscellaneous configurable options 223 */ 224 #define V_PROMPT "AM3517_EVM # " 225 226 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 227 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 228 #define CONFIG_SYS_PROMPT V_PROMPT 229 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 230 /* Print Buffer Size */ 231 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 232 sizeof(CONFIG_SYS_PROMPT) + 16) 233 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 234 /* args */ 235 /* Boot Argument Buffer Size */ 236 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 237 /* memtest works on */ 238 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 239 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 240 0x01F00000) /* 31MB */ 241 242 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 243 /* address */ 244 245 /* 246 * AM3517 has 12 GP timers, they can be driven by the system clock 247 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 248 * This rate is divided by a local divisor. 249 */ 250 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 251 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 252 253 /*----------------------------------------------------------------------- 254 * Physical Memory Map 255 */ 256 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 257 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 258 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 259 260 /*----------------------------------------------------------------------- 261 * FLASH and environment organization 262 */ 263 264 /* **** PISMO SUPPORT *** */ 265 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 266 /* on one chip */ 267 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 268 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 269 270 #if defined(CONFIG_CMD_NAND) 271 #define CONFIG_SYS_FLASH_BASE NAND_BASE 272 #endif 273 274 /* Monitor at start of flash */ 275 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 276 277 #define CONFIG_NAND_OMAP_GPMC 278 #define CONFIG_ENV_IS_IN_NAND 1 279 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 280 281 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 282 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 283 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 284 285 /*----------------------------------------------------------------------- 286 * CFI FLASH driver setup 287 */ 288 /* timeout values are in ticks */ 289 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 290 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 291 292 /* Flash banks JFFS2 should use */ 293 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 294 CONFIG_SYS_MAX_NAND_DEVICE) 295 #define CONFIG_SYS_JFFS2_MEM_NAND 296 /* use flash_info[2] */ 297 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 298 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 299 300 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 301 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 302 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 303 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 304 CONFIG_SYS_INIT_RAM_SIZE - \ 305 GENERATED_GBL_DATA_SIZE) 306 307 /* Defines for SPL */ 308 #define CONFIG_SPL_FRAMEWORK 309 #define CONFIG_SPL_BOARD_INIT 310 #define CONFIG_SPL_NAND_SIMPLE 311 #define CONFIG_SPL_TEXT_BASE 0x40200800 312 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 313 314 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 315 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 316 317 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 318 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 319 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 320 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 321 322 #define CONFIG_SPL_LIBCOMMON_SUPPORT 323 #define CONFIG_SPL_LIBDISK_SUPPORT 324 #define CONFIG_SPL_I2C_SUPPORT 325 #define CONFIG_SPL_LIBGENERIC_SUPPORT 326 #define CONFIG_SPL_MMC_SUPPORT 327 #define CONFIG_SPL_FAT_SUPPORT 328 #define CONFIG_SPL_SERIAL_SUPPORT 329 #define CONFIG_SPL_NAND_SUPPORT 330 #define CONFIG_SPL_NAND_BASE 331 #define CONFIG_SPL_NAND_DRIVERS 332 #define CONFIG_SPL_NAND_ECC 333 #define CONFIG_SPL_POWER_SUPPORT 334 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 335 336 /* NAND boot config */ 337 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 338 #define CONFIG_SYS_NAND_PAGE_COUNT 64 339 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 340 #define CONFIG_SYS_NAND_OOBSIZE 64 341 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 342 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 343 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 344 10, 11, 12, 13} 345 #define CONFIG_SYS_NAND_ECCSIZE 512 346 #define CONFIG_SYS_NAND_ECCBYTES 3 347 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 348 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 349 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 350 351 /* 352 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 353 * 64 bytes before this address should be set aside for u-boot.img's 354 * header. That is 0x800FFFC0--0x80100000 should not be used for any 355 * other needs. 356 */ 357 #define CONFIG_SYS_TEXT_BASE 0x80100000 358 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 359 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 360 361 #endif /* __CONFIG_H */ 362