1 /* 2 * am3517_evm.h - Default configuration for AM3517 EVM board. 3 * 4 * Author: Vaibhav Hiremath <hvaibhav@ti.com> 5 * 6 * Based on omap3_evm_config.h 7 * 8 * Copyright (C) 2010 Texas Instruments Incorporated 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 21 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ 22 #define CONFIG_OMAP_COMMON 23 24 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 25 26 #include <asm/arch/cpu.h> /* get chip and board defs */ 27 #include <asm/arch/omap3.h> 28 29 /* 30 * Display CPU and Board information 31 */ 32 #define CONFIG_DISPLAY_CPUINFO 1 33 #define CONFIG_DISPLAY_BOARDINFO 1 34 35 /* Clock Defines */ 36 #define V_OSCK 26000000 /* Clock output from T2 */ 37 #define V_SCLK (V_OSCK >> 1) 38 39 #define CONFIG_MISC_INIT_R 40 41 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 42 #define CONFIG_SETUP_MEMORY_TAGS 1 43 #define CONFIG_INITRD_TAG 1 44 #define CONFIG_REVISION_TAG 1 45 46 /* 47 * Size of malloc() pool 48 */ 49 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 50 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 51 /* 52 * DDR related 53 */ 54 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 55 56 /* 57 * Hardware drivers 58 */ 59 60 /* 61 * OMAP GPIO configuration 62 */ 63 #define CONFIG_OMAP_GPIO 64 65 /* 66 * NS16550 Configuration 67 */ 68 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 70 #define CONFIG_SYS_NS16550 71 #define CONFIG_SYS_NS16550_SERIAL 72 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 73 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 74 75 /* 76 * select serial console configuration 77 */ 78 #define CONFIG_CONS_INDEX 3 79 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 80 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ 81 82 /* allow to overwrite serial and ethaddr */ 83 #define CONFIG_ENV_OVERWRITE 84 #define CONFIG_BAUDRATE 115200 85 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 86 115200} 87 #define CONFIG_MMC 1 88 #define CONFIG_GENERIC_MMC 1 89 #define CONFIG_OMAP_HSMMC 1 90 #define CONFIG_DOS_PARTITION 1 91 92 /* 93 * USB configuration 94 * Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard 95 * Enable CONFIG_MUSB_GADGET for Device functionalities. 96 */ 97 #define CONFIG_USB_MUSB_AM35X 98 #define CONFIG_MUSB_HOST 99 #define CONFIG_MUSB_PIO_ONLY 100 101 #ifdef CONFIG_USB_MUSB_AM35X 102 103 #ifdef CONFIG_MUSB_HOST 104 #define CONFIG_CMD_USB 105 106 #define CONFIG_USB_STORAGE 107 #define CONGIG_CMD_STORAGE 108 #define CONFIG_CMD_FAT 109 110 #ifdef CONFIG_USB_KEYBOARD 111 #define CONFIG_SYS_USB_EVENT_POLL 112 #define CONFIG_PREBOOT "usb start" 113 #endif /* CONFIG_USB_KEYBOARD */ 114 115 #endif /* CONFIG_MUSB_HOST */ 116 117 #ifdef CONFIG_MUSB_GADGET 118 #define CONFIG_USB_GADGET_DUALSPEED 119 #define CONFIG_USB_ETHER 120 #define CONFIG_USB_ETH_RNDIS 121 #endif /* CONFIG_MUSB_GADGET */ 122 123 #endif /* CONFIG_USB_MUSB_AM35X */ 124 125 /* commands to include */ 126 #include <config_cmd_default.h> 127 128 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 129 #define CONFIG_CMD_FAT /* FAT support */ 130 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 131 132 #define CONFIG_CMD_I2C /* I2C serial bus support */ 133 #define CONFIG_CMD_MMC /* MMC support */ 134 #define CONFIG_CMD_NAND /* NAND support */ 135 #define CONFIG_CMD_DHCP 136 #undef CONFIG_CMD_PING 137 138 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 139 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 140 #undef CONFIG_CMD_IMI /* iminfo */ 141 #undef CONFIG_CMD_IMLS /* List all found images */ 142 143 #define CONFIG_SYS_NO_FLASH 144 #define CONFIG_SYS_I2C 145 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 146 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 147 #define CONFIG_SYS_I2C_OMAP34XX 148 149 /* 150 * Ethernet 151 */ 152 #define CONFIG_DRIVER_TI_EMAC 153 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 154 #define CONFIG_MII 155 #define CONFIG_BOOTP_DEFAULT 156 #define CONFIG_BOOTP_DNS 157 #define CONFIG_BOOTP_DNS2 158 #define CONFIG_BOOTP_SEND_HOSTNAME 159 #define CONFIG_NET_RETRY_COUNT 10 160 161 /* 162 * Board NAND Info. 163 */ 164 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 165 /* to access nand */ 166 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 167 /* to access */ 168 /* nand at CS0 */ 169 170 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 171 /* NAND devices */ 172 #define CONFIG_JFFS2_NAND 173 /* nand device jffs2 lives on */ 174 #define CONFIG_JFFS2_DEV "nand0" 175 /* start of jffs2 partition */ 176 #define CONFIG_JFFS2_PART_OFFSET 0x680000 177 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 178 179 /* Environment information */ 180 #define CONFIG_BOOTDELAY 10 181 182 #define CONFIG_BOOTFILE "uImage" 183 184 #define CONFIG_EXTRA_ENV_SETTINGS \ 185 "loadaddr=0x82000000\0" \ 186 "console=ttyO2,115200n8\0" \ 187 "mmcdev=0\0" \ 188 "mmcargs=setenv bootargs console=${console} " \ 189 "root=/dev/mmcblk0p2 rw rootwait\0" \ 190 "nandargs=setenv bootargs console=${console} " \ 191 "root=/dev/mtdblock4 rw " \ 192 "rootfstype=jffs2\0" \ 193 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 194 "bootscript=echo Running bootscript from mmc ...; " \ 195 "source ${loadaddr}\0" \ 196 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 197 "mmcboot=echo Booting from mmc ...; " \ 198 "run mmcargs; " \ 199 "bootm ${loadaddr}\0" \ 200 "nandboot=echo Booting from nand ...; " \ 201 "run nandargs; " \ 202 "nand read ${loadaddr} 280000 400000; " \ 203 "bootm ${loadaddr}\0" \ 204 205 #define CONFIG_BOOTCOMMAND \ 206 "mmc dev ${mmcdev}; if mmc rescan; then " \ 207 "if run loadbootscript; then " \ 208 "run bootscript; " \ 209 "else " \ 210 "if run loaduimage; then " \ 211 "run mmcboot; " \ 212 "else run nandboot; " \ 213 "fi; " \ 214 "fi; " \ 215 "else run nandboot; fi" 216 217 #define CONFIG_AUTO_COMPLETE 1 218 /* 219 * Miscellaneous configurable options 220 */ 221 #define V_PROMPT "AM3517_EVM # " 222 223 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 224 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 225 #define CONFIG_SYS_PROMPT V_PROMPT 226 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 227 /* Print Buffer Size */ 228 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 229 sizeof(CONFIG_SYS_PROMPT) + 16) 230 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 231 /* args */ 232 /* Boot Argument Buffer Size */ 233 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 234 /* memtest works on */ 235 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 236 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 237 0x01F00000) /* 31MB */ 238 239 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 240 /* address */ 241 242 /* 243 * AM3517 has 12 GP timers, they can be driven by the system clock 244 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 245 * This rate is divided by a local divisor. 246 */ 247 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 248 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 249 250 /*----------------------------------------------------------------------- 251 * Physical Memory Map 252 */ 253 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 254 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 255 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 256 257 /*----------------------------------------------------------------------- 258 * FLASH and environment organization 259 */ 260 261 /* **** PISMO SUPPORT *** */ 262 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 263 /* on one chip */ 264 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 265 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 266 267 #if defined(CONFIG_CMD_NAND) 268 #define CONFIG_SYS_FLASH_BASE NAND_BASE 269 #endif 270 271 /* Monitor at start of flash */ 272 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 273 274 #define CONFIG_NAND_OMAP_GPMC 275 #define CONFIG_ENV_IS_IN_NAND 1 276 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 277 278 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 279 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 280 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 281 282 /*----------------------------------------------------------------------- 283 * CFI FLASH driver setup 284 */ 285 /* timeout values are in ticks */ 286 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 287 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 288 289 /* Flash banks JFFS2 should use */ 290 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 291 CONFIG_SYS_MAX_NAND_DEVICE) 292 #define CONFIG_SYS_JFFS2_MEM_NAND 293 /* use flash_info[2] */ 294 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 295 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 296 297 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 298 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 299 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 300 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 301 CONFIG_SYS_INIT_RAM_SIZE - \ 302 GENERATED_GBL_DATA_SIZE) 303 304 /* Defines for SPL */ 305 #define CONFIG_SPL_FRAMEWORK 306 #define CONFIG_SPL_BOARD_INIT 307 #define CONFIG_SPL_NAND_SIMPLE 308 #define CONFIG_SPL_TEXT_BASE 0x40200800 309 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 310 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 311 312 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 313 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 314 315 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 316 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 317 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 318 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 319 320 #define CONFIG_SPL_LIBCOMMON_SUPPORT 321 #define CONFIG_SPL_LIBDISK_SUPPORT 322 #define CONFIG_SPL_I2C_SUPPORT 323 #define CONFIG_SPL_LIBGENERIC_SUPPORT 324 #define CONFIG_SPL_MMC_SUPPORT 325 #define CONFIG_SPL_FAT_SUPPORT 326 #define CONFIG_SPL_SERIAL_SUPPORT 327 #define CONFIG_SPL_NAND_SUPPORT 328 #define CONFIG_SPL_NAND_BASE 329 #define CONFIG_SPL_NAND_DRIVERS 330 #define CONFIG_SPL_NAND_ECC 331 #define CONFIG_SPL_POWER_SUPPORT 332 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 333 334 /* NAND boot config */ 335 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 336 #define CONFIG_SYS_NAND_PAGE_COUNT 64 337 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 338 #define CONFIG_SYS_NAND_OOBSIZE 64 339 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 340 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 341 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 342 10, 11, 12, 13} 343 #define CONFIG_SYS_NAND_ECCSIZE 512 344 #define CONFIG_SYS_NAND_ECCBYTES 3 345 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 346 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 347 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 348 349 /* 350 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 351 * 64 bytes before this address should be set aside for u-boot.img's 352 * header. That is 0x800FFFC0--0x80100000 should not be used for any 353 * other needs. 354 */ 355 #define CONFIG_SYS_TEXT_BASE 0x80100000 356 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 357 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 358 359 #endif /* __CONFIG_H */ 360