1 /* 2 * am3517_evm.h - Default configuration for AM3517 EVM board. 3 * 4 * Author: Vaibhav Hiremath <hvaibhav@ti.com> 5 * 6 * Based on omap3_evm_config.h 7 * 8 * Copyright (C) 2010 Texas Instruments Incorporated 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 21 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ 22 #define CONFIG_OMAP_COMMON 23 24 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 25 26 #include <asm/arch/cpu.h> /* get chip and board defs */ 27 #include <asm/arch/omap3.h> 28 29 /* 30 * Display CPU and Board information 31 */ 32 #define CONFIG_DISPLAY_CPUINFO 1 33 #define CONFIG_DISPLAY_BOARDINFO 1 34 35 /* Clock Defines */ 36 #define V_OSCK 26000000 /* Clock output from T2 */ 37 #define V_SCLK (V_OSCK >> 1) 38 39 #define CONFIG_MISC_INIT_R 40 41 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 42 #define CONFIG_SETUP_MEMORY_TAGS 1 43 #define CONFIG_INITRD_TAG 1 44 #define CONFIG_REVISION_TAG 1 45 46 /* 47 * Size of malloc() pool 48 */ 49 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 50 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 51 /* 52 * DDR related 53 */ 54 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 55 56 /* 57 * Hardware drivers 58 */ 59 60 /* 61 * NS16550 Configuration 62 */ 63 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 64 65 #define CONFIG_SYS_NS16550 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 69 70 /* 71 * select serial console configuration 72 */ 73 #define CONFIG_CONS_INDEX 3 74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ 76 77 /* allow to overwrite serial and ethaddr */ 78 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_BAUDRATE 115200 80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 81 115200} 82 #define CONFIG_MMC 1 83 #define CONFIG_GENERIC_MMC 1 84 #define CONFIG_OMAP_HSMMC 1 85 #define CONFIG_DOS_PARTITION 1 86 87 /* 88 * USB configuration 89 * Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard 90 * Enable CONFIG_MUSB_GADGET for Device functionalities. 91 */ 92 #define CONFIG_USB_MUSB_AM35X 93 #define CONFIG_MUSB_HOST 94 #define CONFIG_MUSB_PIO_ONLY 95 96 #ifdef CONFIG_USB_MUSB_AM35X 97 98 #ifdef CONFIG_MUSB_HOST 99 #define CONFIG_CMD_USB 100 101 #define CONFIG_USB_STORAGE 102 #define CONGIG_CMD_STORAGE 103 #define CONFIG_CMD_FAT 104 105 #ifdef CONFIG_USB_KEYBOARD 106 #define CONFIG_SYS_USB_EVENT_POLL 107 #define CONFIG_PREBOOT "usb start" 108 #endif /* CONFIG_USB_KEYBOARD */ 109 110 #endif /* CONFIG_MUSB_HOST */ 111 112 #ifdef CONFIG_MUSB_GADGET 113 #define CONFIG_USB_GADGET_DUALSPEED 114 #define CONFIG_USB_ETHER 115 #define CONFIG_USB_ETH_RNDIS 116 #endif /* CONFIG_MUSB_GADGET */ 117 118 #endif /* CONFIG_USB_MUSB_AM35X */ 119 120 /* commands to include */ 121 #include <config_cmd_default.h> 122 123 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 124 #define CONFIG_CMD_FAT /* FAT support */ 125 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 126 127 #define CONFIG_CMD_I2C /* I2C serial bus support */ 128 #define CONFIG_CMD_MMC /* MMC support */ 129 #define CONFIG_CMD_NAND /* NAND support */ 130 #define CONFIG_CMD_DHCP 131 #undef CONFIG_CMD_PING 132 133 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 134 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 135 #undef CONFIG_CMD_IMI /* iminfo */ 136 #undef CONFIG_CMD_IMLS /* List all found images */ 137 138 #define CONFIG_SYS_NO_FLASH 139 #define CONFIG_HARD_I2C 1 140 #define CONFIG_SYS_I2C_SPEED 100000 141 #define CONFIG_SYS_I2C_SLAVE 1 142 #define CONFIG_DRIVER_OMAP34XX_I2C 1 143 144 #undef CONFIG_CMD_NET 145 #undef CONFIG_CMD_NFS 146 /* 147 * Board NAND Info. 148 */ 149 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 150 /* to access nand */ 151 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 152 /* to access */ 153 /* nand at CS0 */ 154 155 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 156 /* NAND devices */ 157 #define CONFIG_JFFS2_NAND 158 /* nand device jffs2 lives on */ 159 #define CONFIG_JFFS2_DEV "nand0" 160 /* start of jffs2 partition */ 161 #define CONFIG_JFFS2_PART_OFFSET 0x680000 162 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 163 164 /* Environment information */ 165 #define CONFIG_BOOTDELAY 10 166 167 #define CONFIG_BOOTFILE "uImage" 168 169 #define CONFIG_EXTRA_ENV_SETTINGS \ 170 "loadaddr=0x82000000\0" \ 171 "console=ttyO2,115200n8\0" \ 172 "mmcdev=0\0" \ 173 "mmcargs=setenv bootargs console=${console} " \ 174 "root=/dev/mmcblk0p2 rw rootwait\0" \ 175 "nandargs=setenv bootargs console=${console} " \ 176 "root=/dev/mtdblock4 rw " \ 177 "rootfstype=jffs2\0" \ 178 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 179 "bootscript=echo Running bootscript from mmc ...; " \ 180 "source ${loadaddr}\0" \ 181 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 182 "mmcboot=echo Booting from mmc ...; " \ 183 "run mmcargs; " \ 184 "bootm ${loadaddr}\0" \ 185 "nandboot=echo Booting from nand ...; " \ 186 "run nandargs; " \ 187 "nand read ${loadaddr} 280000 400000; " \ 188 "bootm ${loadaddr}\0" \ 189 190 #define CONFIG_BOOTCOMMAND \ 191 "mmc dev ${mmcdev}; if mmc rescan; then " \ 192 "if run loadbootscript; then " \ 193 "run bootscript; " \ 194 "else " \ 195 "if run loaduimage; then " \ 196 "run mmcboot; " \ 197 "else run nandboot; " \ 198 "fi; " \ 199 "fi; " \ 200 "else run nandboot; fi" 201 202 #define CONFIG_AUTO_COMPLETE 1 203 /* 204 * Miscellaneous configurable options 205 */ 206 #define V_PROMPT "AM3517_EVM # " 207 208 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 209 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 210 #define CONFIG_SYS_PROMPT V_PROMPT 211 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 212 /* Print Buffer Size */ 213 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 214 sizeof(CONFIG_SYS_PROMPT) + 16) 215 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 216 /* args */ 217 /* Boot Argument Buffer Size */ 218 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 219 /* memtest works on */ 220 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 221 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 222 0x01F00000) /* 31MB */ 223 224 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 225 /* address */ 226 227 /* 228 * AM3517 has 12 GP timers, they can be driven by the system clock 229 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 230 * This rate is divided by a local divisor. 231 */ 232 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 233 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 234 #define CONFIG_SYS_HZ 1000 235 236 /*----------------------------------------------------------------------- 237 * Physical Memory Map 238 */ 239 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 240 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 241 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 242 243 /*----------------------------------------------------------------------- 244 * FLASH and environment organization 245 */ 246 247 /* **** PISMO SUPPORT *** */ 248 249 /* Configure the PISMO */ 250 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 251 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 252 253 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 254 /* on one chip */ 255 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 256 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 257 258 #if defined(CONFIG_CMD_NAND) 259 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 260 #endif 261 262 /* Monitor at start of flash */ 263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 264 265 #define CONFIG_NAND_OMAP_GPMC 266 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 267 #define CONFIG_ENV_IS_IN_NAND 1 268 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 269 270 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 271 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 272 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 273 274 /*----------------------------------------------------------------------- 275 * CFI FLASH driver setup 276 */ 277 /* timeout values are in ticks */ 278 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 279 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 280 281 /* Flash banks JFFS2 should use */ 282 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 283 CONFIG_SYS_MAX_NAND_DEVICE) 284 #define CONFIG_SYS_JFFS2_MEM_NAND 285 /* use flash_info[2] */ 286 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 287 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 288 289 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 290 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 291 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 292 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 293 CONFIG_SYS_INIT_RAM_SIZE - \ 294 GENERATED_GBL_DATA_SIZE) 295 296 /* Defines for SPL */ 297 #define CONFIG_SPL 298 #define CONFIG_SPL_FRAMEWORK 299 #define CONFIG_SPL_BOARD_INIT 300 #define CONFIG_SPL_NAND_SIMPLE 301 #define CONFIG_SPL_TEXT_BASE 0x40200800 302 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 303 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 304 305 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 306 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 307 308 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 309 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 310 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 311 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 312 313 #define CONFIG_SPL_LIBCOMMON_SUPPORT 314 #define CONFIG_SPL_LIBDISK_SUPPORT 315 #define CONFIG_SPL_I2C_SUPPORT 316 #define CONFIG_SPL_LIBGENERIC_SUPPORT 317 #define CONFIG_SPL_MMC_SUPPORT 318 #define CONFIG_SPL_FAT_SUPPORT 319 #define CONFIG_SPL_SERIAL_SUPPORT 320 #define CONFIG_SPL_NAND_SUPPORT 321 #define CONFIG_SPL_NAND_BASE 322 #define CONFIG_SPL_NAND_DRIVERS 323 #define CONFIG_SPL_NAND_ECC 324 #define CONFIG_SPL_POWER_SUPPORT 325 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 326 327 /* NAND boot config */ 328 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 329 #define CONFIG_SYS_NAND_PAGE_COUNT 64 330 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 331 #define CONFIG_SYS_NAND_OOBSIZE 64 332 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 333 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 334 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 335 10, 11, 12, 13} 336 #define CONFIG_SYS_NAND_ECCSIZE 512 337 #define CONFIG_SYS_NAND_ECCBYTES 3 338 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 339 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 340 341 /* 342 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 343 * 64 bytes before this address should be set aside for u-boot.img's 344 * header. That is 0x800FFFC0--0x80100000 should not be used for any 345 * other needs. 346 */ 347 #define CONFIG_SYS_TEXT_BASE 0x80100000 348 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 349 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 350 351 #endif /* __CONFIG_H */ 352