1 /* 2 * am3517_evm.h - Default configuration for AM3517 EVM board. 3 * 4 * Author: Vaibhav Hiremath <hvaibhav@ti.com> 5 * 6 * Based on omap3_evm_config.h 7 * 8 * Copyright (C) 2010 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 32 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 33 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ 34 35 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 36 37 #include <asm/arch/cpu.h> /* get chip and board defs */ 38 #include <asm/arch/omap3.h> 39 40 /* 41 * Display CPU and Board information 42 */ 43 #define CONFIG_DISPLAY_CPUINFO 1 44 #define CONFIG_DISPLAY_BOARDINFO 1 45 46 /* Clock Defines */ 47 #define V_OSCK 26000000 /* Clock output from T2 */ 48 #define V_SCLK (V_OSCK >> 1) 49 50 #define CONFIG_MISC_INIT_R 51 52 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 53 #define CONFIG_SETUP_MEMORY_TAGS 1 54 #define CONFIG_INITRD_TAG 1 55 #define CONFIG_REVISION_TAG 1 56 57 /* 58 * Size of malloc() pool 59 */ 60 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 61 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 62 /* 63 * DDR related 64 */ 65 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 66 67 /* 68 * Hardware drivers 69 */ 70 71 /* 72 * NS16550 Configuration 73 */ 74 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 75 76 #define CONFIG_SYS_NS16550 77 #define CONFIG_SYS_NS16550_SERIAL 78 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 79 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 80 81 /* 82 * select serial console configuration 83 */ 84 #define CONFIG_CONS_INDEX 3 85 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 86 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ 87 88 /* allow to overwrite serial and ethaddr */ 89 #define CONFIG_ENV_OVERWRITE 90 #define CONFIG_BAUDRATE 115200 91 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 92 115200} 93 #define CONFIG_MMC 1 94 #define CONFIG_GENERIC_MMC 1 95 #define CONFIG_OMAP_HSMMC 1 96 #define CONFIG_DOS_PARTITION 1 97 98 /* 99 * USB configuration 100 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 101 * Enable CONFIG_MUSB_UDC for Device functionalities. 102 */ 103 #define CONFIG_USB_AM35X 1 104 #define CONFIG_MUSB_HCD 1 105 106 #ifdef CONFIG_USB_AM35X 107 108 #ifdef CONFIG_MUSB_HCD 109 #define CONFIG_CMD_USB 110 111 #define CONFIG_USB_STORAGE 112 #define CONGIG_CMD_STORAGE 113 #define CONFIG_CMD_FAT 114 115 #ifdef CONFIG_USB_KEYBOARD 116 #define CONFIG_SYS_USB_EVENT_POLL 117 #define CONFIG_PREBOOT "usb start" 118 #endif /* CONFIG_USB_KEYBOARD */ 119 120 #endif /* CONFIG_MUSB_HCD */ 121 122 #ifdef CONFIG_MUSB_UDC 123 /* USB device configuration */ 124 #define CONFIG_USB_DEVICE 1 125 #define CONFIG_USB_TTY 1 126 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 127 /* Change these to suit your needs */ 128 #define CONFIG_USBD_VENDORID 0x0451 129 #define CONFIG_USBD_PRODUCTID 0x5678 130 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 131 #define CONFIG_USBD_PRODUCT_NAME "AM3517EVM" 132 #endif /* CONFIG_MUSB_UDC */ 133 134 #endif /* CONFIG_USB_AM35X */ 135 136 /* commands to include */ 137 #include <config_cmd_default.h> 138 139 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 140 #define CONFIG_CMD_FAT /* FAT support */ 141 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 142 143 #define CONFIG_CMD_I2C /* I2C serial bus support */ 144 #define CONFIG_CMD_MMC /* MMC support */ 145 #define CONFIG_CMD_NAND /* NAND support */ 146 #define CONFIG_CMD_DHCP 147 #undef CONFIG_CMD_PING 148 149 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 150 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 151 #undef CONFIG_CMD_IMI /* iminfo */ 152 #undef CONFIG_CMD_IMLS /* List all found images */ 153 154 #define CONFIG_SYS_NO_FLASH 155 #define CONFIG_HARD_I2C 1 156 #define CONFIG_SYS_I2C_SPEED 100000 157 #define CONFIG_SYS_I2C_SLAVE 1 158 #define CONFIG_SYS_I2C_BUS 0 159 #define CONFIG_SYS_I2C_BUS_SELECT 1 160 #define CONFIG_DRIVER_OMAP34XX_I2C 1 161 162 #undef CONFIG_CMD_NET 163 #undef CONFIG_CMD_NFS 164 /* 165 * Board NAND Info. 166 */ 167 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 168 /* to access nand */ 169 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 170 /* to access */ 171 /* nand at CS0 */ 172 173 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 174 /* NAND devices */ 175 #define CONFIG_JFFS2_NAND 176 /* nand device jffs2 lives on */ 177 #define CONFIG_JFFS2_DEV "nand0" 178 /* start of jffs2 partition */ 179 #define CONFIG_JFFS2_PART_OFFSET 0x680000 180 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 181 182 /* Environment information */ 183 #define CONFIG_BOOTDELAY 10 184 185 #define CONFIG_BOOTFILE "uImage" 186 187 #define CONFIG_EXTRA_ENV_SETTINGS \ 188 "loadaddr=0x82000000\0" \ 189 "console=ttyO2,115200n8\0" \ 190 "mmcdev=0\0" \ 191 "mmcargs=setenv bootargs console=${console} " \ 192 "root=/dev/mmcblk0p2 rw rootwait\0" \ 193 "nandargs=setenv bootargs console=${console} " \ 194 "root=/dev/mtdblock4 rw " \ 195 "rootfstype=jffs2\0" \ 196 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 197 "bootscript=echo Running bootscript from mmc ...; " \ 198 "source ${loadaddr}\0" \ 199 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 200 "mmcboot=echo Booting from mmc ...; " \ 201 "run mmcargs; " \ 202 "bootm ${loadaddr}\0" \ 203 "nandboot=echo Booting from nand ...; " \ 204 "run nandargs; " \ 205 "nand read ${loadaddr} 280000 400000; " \ 206 "bootm ${loadaddr}\0" \ 207 208 #define CONFIG_BOOTCOMMAND \ 209 "mmc dev ${mmcdev}; if mmc rescan; then " \ 210 "if run loadbootscript; then " \ 211 "run bootscript; " \ 212 "else " \ 213 "if run loaduimage; then " \ 214 "run mmcboot; " \ 215 "else run nandboot; " \ 216 "fi; " \ 217 "fi; " \ 218 "else run nandboot; fi" 219 220 #define CONFIG_AUTO_COMPLETE 1 221 /* 222 * Miscellaneous configurable options 223 */ 224 #define V_PROMPT "AM3517_EVM # " 225 226 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 227 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 228 #define CONFIG_SYS_PROMPT V_PROMPT 229 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 230 /* Print Buffer Size */ 231 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 232 sizeof(CONFIG_SYS_PROMPT) + 16) 233 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 234 /* args */ 235 /* Boot Argument Buffer Size */ 236 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 237 /* memtest works on */ 238 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 239 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 240 0x01F00000) /* 31MB */ 241 242 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 243 /* address */ 244 245 /* 246 * AM3517 has 12 GP timers, they can be driven by the system clock 247 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 248 * This rate is divided by a local divisor. 249 */ 250 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 251 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 252 #define CONFIG_SYS_HZ 1000 253 254 /*----------------------------------------------------------------------- 255 * Physical Memory Map 256 */ 257 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 258 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 259 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 260 261 /*----------------------------------------------------------------------- 262 * FLASH and environment organization 263 */ 264 265 /* **** PISMO SUPPORT *** */ 266 267 /* Configure the PISMO */ 268 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 269 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 270 271 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 272 /* on one chip */ 273 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 274 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 275 276 #if defined(CONFIG_CMD_NAND) 277 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 278 #endif 279 280 /* Monitor at start of flash */ 281 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 282 283 #define CONFIG_NAND_OMAP_GPMC 284 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 285 #define CONFIG_ENV_IS_IN_NAND 1 286 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 287 288 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 289 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 290 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 291 292 /*----------------------------------------------------------------------- 293 * CFI FLASH driver setup 294 */ 295 /* timeout values are in ticks */ 296 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 297 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 298 299 /* Flash banks JFFS2 should use */ 300 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 301 CONFIG_SYS_MAX_NAND_DEVICE) 302 #define CONFIG_SYS_JFFS2_MEM_NAND 303 /* use flash_info[2] */ 304 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 305 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 306 307 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 308 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 309 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 310 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 311 CONFIG_SYS_INIT_RAM_SIZE - \ 312 GENERATED_GBL_DATA_SIZE) 313 314 /* Defines for SPL */ 315 #define CONFIG_SPL 316 #define CONFIG_SPL_FRAMEWORK 317 #define CONFIG_SPL_BOARD_INIT 318 #define CONFIG_SPL_NAND_SIMPLE 319 #define CONFIG_SPL_TEXT_BASE 0x40200800 320 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 321 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 322 323 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 324 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 325 326 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 327 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 328 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 329 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 330 331 #define CONFIG_SPL_LIBCOMMON_SUPPORT 332 #define CONFIG_SPL_LIBDISK_SUPPORT 333 #define CONFIG_SPL_I2C_SUPPORT 334 #define CONFIG_SPL_LIBGENERIC_SUPPORT 335 #define CONFIG_SPL_MMC_SUPPORT 336 #define CONFIG_SPL_FAT_SUPPORT 337 #define CONFIG_SPL_SERIAL_SUPPORT 338 #define CONFIG_SPL_NAND_SUPPORT 339 #define CONFIG_SPL_POWER_SUPPORT 340 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 341 342 /* NAND boot config */ 343 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 344 #define CONFIG_SYS_NAND_PAGE_COUNT 64 345 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 346 #define CONFIG_SYS_NAND_OOBSIZE 64 347 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 348 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 349 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 350 10, 11, 12, 13} 351 #define CONFIG_SYS_NAND_ECCSIZE 512 352 #define CONFIG_SYS_NAND_ECCBYTES 3 353 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 354 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 355 356 /* 357 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 358 * 64 bytes before this address should be set aside for u-boot.img's 359 * header. That is 0x800FFFC0--0x80100000 should not be used for any 360 * other needs. 361 */ 362 #define CONFIG_SYS_TEXT_BASE 0x80100000 363 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 364 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 365 366 #endif /* __CONFIG_H */ 367