1 /* 2 * am3517_evm.h - Default configuration for AM3517 EVM board. 3 * 4 * Author: Vaibhav Hiremath <hvaibhav@ti.com> 5 * 6 * Based on omap3_evm_config.h 7 * 8 * Copyright (C) 2010 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ 32 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 33 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 34 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ 35 36 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 37 38 #include <asm/arch/cpu.h> /* get chip and board defs */ 39 #include <asm/arch/omap3.h> 40 41 /* 42 * Display CPU and Board information 43 */ 44 #define CONFIG_DISPLAY_CPUINFO 1 45 #define CONFIG_DISPLAY_BOARDINFO 1 46 47 /* Clock Defines */ 48 #define V_OSCK 26000000 /* Clock output from T2 */ 49 #define V_SCLK (V_OSCK >> 1) 50 51 #undef CONFIG_USE_IRQ /* no support for IRQs */ 52 #define CONFIG_MISC_INIT_R 53 54 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 55 #define CONFIG_SETUP_MEMORY_TAGS 1 56 #define CONFIG_INITRD_TAG 1 57 #define CONFIG_REVISION_TAG 1 58 59 /* 60 * Size of malloc() pool 61 */ 62 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 63 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 64 /* 65 * DDR related 66 */ 67 #define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */ 68 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 69 70 /* 71 * Hardware drivers 72 */ 73 74 /* 75 * NS16550 Configuration 76 */ 77 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 78 79 #define CONFIG_SYS_NS16550 80 #define CONFIG_SYS_NS16550_SERIAL 81 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 82 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 83 84 /* 85 * select serial console configuration 86 */ 87 #define CONFIG_CONS_INDEX 3 88 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 89 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ 90 91 /* allow to overwrite serial and ethaddr */ 92 #define CONFIG_ENV_OVERWRITE 93 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 95 115200} 96 #define CONFIG_MMC 1 97 #define CONFIG_OMAP3_MMC 1 98 #define CONFIG_DOS_PARTITION 1 99 100 /* 101 * USB configuration 102 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 103 * Enable CONFIG_MUSB_UDC for Device functionalities. 104 */ 105 #define CONFIG_USB_AM35X 1 106 #define CONFIG_MUSB_HCD 1 107 108 #ifdef CONFIG_USB_AM35X 109 110 #ifdef CONFIG_MUSB_HCD 111 #define CONFIG_CMD_USB 112 113 #define CONFIG_USB_STORAGE 114 #define CONGIG_CMD_STORAGE 115 #define CONFIG_CMD_FAT 116 117 #ifdef CONFIG_USB_KEYBOARD 118 #define CONFIG_SYS_USB_EVENT_POLL 119 #define CONFIG_PREBOOT "usb start" 120 #endif /* CONFIG_USB_KEYBOARD */ 121 122 #endif /* CONFIG_MUSB_HCD */ 123 124 #ifdef CONFIG_MUSB_UDC 125 /* USB device configuration */ 126 #define CONFIG_USB_DEVICE 1 127 #define CONFIG_USB_TTY 1 128 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 129 /* Change these to suit your needs */ 130 #define CONFIG_USBD_VENDORID 0x0451 131 #define CONFIG_USBD_PRODUCTID 0x5678 132 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 133 #define CONFIG_USBD_PRODUCT_NAME "AM3517EVM" 134 #endif /* CONFIG_MUSB_UDC */ 135 136 #endif /* CONFIG_USB_AM35X */ 137 138 /* commands to include */ 139 #include <config_cmd_default.h> 140 141 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 142 #define CONFIG_CMD_FAT /* FAT support */ 143 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 144 145 #define CONFIG_CMD_I2C /* I2C serial bus support */ 146 #define CONFIG_CMD_MMC /* MMC support */ 147 #define CONFIG_CMD_NAND /* NAND support */ 148 #define CONFIG_CMD_DHCP 149 #define CONFIG_CMD_PING 150 151 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 152 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 153 #undef CONFIG_CMD_IMI /* iminfo */ 154 #undef CONFIG_CMD_IMLS /* List all found images */ 155 156 #define CONFIG_SYS_NO_FLASH 157 #define CONFIG_HARD_I2C 1 158 #define CONFIG_SYS_I2C_SPEED 100000 159 #define CONFIG_SYS_I2C_SLAVE 1 160 #define CONFIG_SYS_I2C_BUS 0 161 #define CONFIG_SYS_I2C_BUS_SELECT 1 162 #define CONFIG_DRIVER_OMAP34XX_I2C 1 163 164 #undef CONFIG_CMD_NET 165 #undef CONFIG_CMD_NFS 166 /* 167 * Board NAND Info. 168 */ 169 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 170 /* to access nand */ 171 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 172 /* to access */ 173 /* nand at CS0 */ 174 175 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 176 /* NAND devices */ 177 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 178 179 #define CONFIG_JFFS2_NAND 180 /* nand device jffs2 lives on */ 181 #define CONFIG_JFFS2_DEV "nand0" 182 /* start of jffs2 partition */ 183 #define CONFIG_JFFS2_PART_OFFSET 0x680000 184 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 185 186 /* Environment information */ 187 #define CONFIG_BOOTDELAY 10 188 189 #define CONFIG_BOOTFILE uImage 190 191 #define CONFIG_EXTRA_ENV_SETTINGS \ 192 "loadaddr=0x82000000\0" \ 193 "console=ttyS2,115200n8\0" \ 194 "mmcargs=setenv bootargs console=${console} " \ 195 "root=/dev/mmcblk0p2 rw " \ 196 "rootfstype=ext3 rootwait\0" \ 197 "nandargs=setenv bootargs console=${console} " \ 198 "root=/dev/mtdblock4 rw " \ 199 "rootfstype=jffs2\0" \ 200 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 201 "bootscript=echo Running bootscript from mmc ...; " \ 202 "source ${loadaddr}\0" \ 203 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 204 "mmcboot=echo Booting from mmc ...; " \ 205 "run mmcargs; " \ 206 "bootm ${loadaddr}\0" \ 207 "nandboot=echo Booting from nand ...; " \ 208 "run nandargs; " \ 209 "nand read ${loadaddr} 280000 400000; " \ 210 "bootm ${loadaddr}\0" \ 211 212 #define CONFIG_BOOTCOMMAND \ 213 "if mmc init; then " \ 214 "if run loadbootscript; then " \ 215 "run bootscript; " \ 216 "else " \ 217 "if run loaduimage; then " \ 218 "run mmcboot; " \ 219 "else run nandboot; " \ 220 "fi; " \ 221 "fi; " \ 222 "else run nandboot; fi" 223 224 #define CONFIG_AUTO_COMPLETE 1 225 /* 226 * Miscellaneous configurable options 227 */ 228 #define V_PROMPT "AM3517_EVM # " 229 230 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 231 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 232 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 233 #define CONFIG_SYS_PROMPT V_PROMPT 234 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 235 /* Print Buffer Size */ 236 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 237 sizeof(CONFIG_SYS_PROMPT) + 16) 238 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 239 /* args */ 240 /* Boot Argument Buffer Size */ 241 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 242 /* memtest works on */ 243 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 244 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 245 0x01F00000) /* 31MB */ 246 247 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 248 /* address */ 249 250 /* 251 * AM3517 has 12 GP timers, they can be driven by the system clock 252 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 253 * This rate is divided by a local divisor. 254 */ 255 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 256 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 257 #define CONFIG_SYS_HZ 1000 258 259 /*----------------------------------------------------------------------- 260 * Stack sizes 261 * 262 * The stack sizes are set up in start.S using the settings below 263 */ 264 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 265 #ifdef CONFIG_USE_IRQ 266 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 267 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 268 #endif 269 270 /*----------------------------------------------------------------------- 271 * Physical Memory Map 272 */ 273 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 274 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 275 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 276 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 277 278 /* SDRAM Bank Allocation method */ 279 #define SDRC_R_B_C 1 280 281 /*----------------------------------------------------------------------- 282 * FLASH and environment organization 283 */ 284 285 /* **** PISMO SUPPORT *** */ 286 287 /* Configure the PISMO */ 288 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 289 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 290 291 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 292 /* on one chip */ 293 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 294 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 295 296 #if defined(CONFIG_CMD_NAND) 297 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 298 #endif 299 300 /* Monitor at start of flash */ 301 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 302 303 #define CONFIG_NAND_OMAP_GPMC 304 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 305 #define CONFIG_ENV_IS_IN_NAND 1 306 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 307 308 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 309 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 310 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 311 312 /*----------------------------------------------------------------------- 313 * CFI FLASH driver setup 314 */ 315 /* timeout values are in ticks */ 316 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 317 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 318 319 /* Flash banks JFFS2 should use */ 320 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 321 CONFIG_SYS_MAX_NAND_DEVICE) 322 #define CONFIG_SYS_JFFS2_MEM_NAND 323 /* use flash_info[2] */ 324 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 325 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 326 327 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 328 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 329 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 330 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 331 CONFIG_SYS_INIT_RAM_SIZE - \ 332 GENERATED_GBL_DATA_SIZE) 333 #endif /* __CONFIG_H */ 334