1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 4 * 5 * Author: Srinath.R <srinath@mistralsolutions.com> 6 * 7 * Based on include/configs/am3517evm.h 8 * 9 * Copyright (C) 2011 Mistral Solutions pvt Ltd 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 19 #include <asm/arch/cpu.h> /* get chip and board defs */ 20 #include <asm/arch/omap.h> 21 22 /* Clock Defines */ 23 #define V_OSCK 26000000 /* Clock output from T2 */ 24 #define V_SCLK (V_OSCK >> 1) 25 26 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 27 #define CONFIG_SETUP_MEMORY_TAGS 1 28 #define CONFIG_INITRD_TAG 1 29 #define CONFIG_REVISION_TAG 1 30 31 /* 32 * Size of malloc() pool 33 */ 34 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 35 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 36 /* initial data */ 37 /* 38 * DDR related 39 */ 40 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 41 42 /* 43 * Hardware drivers 44 */ 45 46 /* 47 * NS16550 Configuration 48 */ 49 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 50 51 #define CONFIG_SYS_NS16550_SERIAL 52 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 53 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 54 55 /* 56 * select serial console configuration 57 */ 58 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 59 60 /* allow to overwrite serial and ethaddr */ 61 #define CONFIG_ENV_OVERWRITE 62 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 63 115200} 64 65 /* 66 * USB configuration 67 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 68 * Enable CONFIG_USB_MUSB_UDC for Device functionalities. 69 */ 70 71 #ifdef CONFIG_USB_AM35X 72 73 #ifdef CONFIG_USB_MUSB_HCD 74 75 #ifdef CONFIG_USB_KEYBOARD 76 #define CONFIG_PREBOOT "usb start" 77 #endif /* CONFIG_USB_KEYBOARD */ 78 79 #endif /* CONFIG_USB_MUSB_HCD */ 80 81 #ifdef CONFIG_USB_MUSB_UDC 82 /* USB device configuration */ 83 #define CONFIG_USB_DEVICE 1 84 #define CONFIG_USB_TTY 1 85 /* Change these to suit your needs */ 86 #define CONFIG_USBD_VENDORID 0x0451 87 #define CONFIG_USBD_PRODUCTID 0x5678 88 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 89 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 90 #endif /* CONFIG_USB_MUSB_UDC */ 91 92 #endif /* CONFIG_USB_AM35X */ 93 94 #define CONFIG_SYS_I2C 95 96 /* 97 * Board NAND Info. 98 */ 99 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 100 /* to access */ 101 /* nand at CS0 */ 102 103 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 104 /* NAND devices */ 105 106 #define CONFIG_JFFS2_NAND 107 /* nand device jffs2 lives on */ 108 #define CONFIG_JFFS2_DEV "nand0" 109 /* start of jffs2 partition */ 110 #define CONFIG_JFFS2_PART_OFFSET 0x680000 111 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 112 113 /* Environment information */ 114 115 #define CONFIG_BOOTFILE "uImage" 116 117 #define CONFIG_EXTRA_ENV_SETTINGS \ 118 "loadaddr=0x82000000\0" \ 119 "console=ttyS2,115200n8\0" \ 120 "mmcdev=0\0" \ 121 "mmcargs=setenv bootargs console=${console} " \ 122 "root=/dev/mmcblk0p2 rw " \ 123 "rootfstype=ext3 rootwait\0" \ 124 "nandargs=setenv bootargs console=${console} " \ 125 "root=/dev/mtdblock4 rw " \ 126 "rootfstype=jffs2\0" \ 127 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 128 "bootscript=echo Running bootscript from mmc ...; " \ 129 "source ${loadaddr}\0" \ 130 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 131 "mmcboot=echo Booting from mmc ...; " \ 132 "run mmcargs; " \ 133 "bootm ${loadaddr}\0" \ 134 "nandboot=echo Booting from nand ...; " \ 135 "run nandargs; " \ 136 "nand read ${loadaddr} 280000 400000; " \ 137 "bootm ${loadaddr}\0" \ 138 139 #define CONFIG_BOOTCOMMAND \ 140 "mmc dev ${mmcdev}; if mmc rescan; then " \ 141 "if run loadbootscript; then " \ 142 "run bootscript; " \ 143 "else " \ 144 "if run loaduimage; then " \ 145 "run mmcboot; " \ 146 "else run nandboot; " \ 147 "fi; " \ 148 "fi; " \ 149 "else run nandboot; fi" 150 151 /* 152 * Miscellaneous configurable options 153 */ 154 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 155 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 156 /* args */ 157 /* memtest works on */ 158 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 159 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 160 0x01F00000) /* 31MB */ 161 162 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 163 /* address */ 164 165 /* 166 * AM3517 has 12 GP timers, they can be driven by the system clock 167 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 168 * This rate is divided by a local divisor. 169 */ 170 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 171 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 172 173 /*----------------------------------------------------------------------- 174 * Physical Memory Map 175 */ 176 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 177 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 178 179 /*----------------------------------------------------------------------- 180 * FLASH and environment organization 181 */ 182 183 /* **** PISMO SUPPORT *** */ 184 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 185 /* on one chip */ 186 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 187 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 188 189 #define CONFIG_SYS_FLASH_BASE NAND_BASE 190 191 /* Monitor at start of flash */ 192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 193 194 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 195 #define CONFIG_ENV_OFFSET 0x260000 196 #define CONFIG_ENV_ADDR 0x260000 197 198 /*----------------------------------------------------------------------- 199 * CFI FLASH driver setup 200 */ 201 /* timeout values are in ticks */ 202 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 203 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 204 205 /* Flash banks JFFS2 should use */ 206 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 207 CONFIG_SYS_MAX_NAND_DEVICE) 208 #define CONFIG_SYS_JFFS2_MEM_NAND 209 /* use flash_info[2] */ 210 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 211 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 212 213 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 214 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 215 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 216 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 217 CONFIG_SYS_INIT_RAM_SIZE - \ 218 GENERATED_GBL_DATA_SIZE) 219 220 /* Defines for SPL */ 221 #define CONFIG_SPL_TEXT_BASE 0x40200800 222 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 223 CONFIG_SPL_TEXT_BASE) 224 225 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 226 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 227 228 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 229 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 230 231 #define CONFIG_SPL_NAND_BASE 232 #define CONFIG_SPL_NAND_DRIVERS 233 #define CONFIG_SPL_NAND_ECC 234 235 /* NAND boot config */ 236 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 237 #define CONFIG_SYS_NAND_PAGE_COUNT 64 238 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 239 #define CONFIG_SYS_NAND_OOBSIZE 64 240 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 241 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 242 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 243 10, 11, 12, 13} 244 #define CONFIG_SYS_NAND_ECCSIZE 512 245 #define CONFIG_SYS_NAND_ECCBYTES 3 246 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 247 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 248 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 249 250 /* 251 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 252 * 64 bytes before this address should be set aside for u-boot.img's 253 * header. That is 0x800FFFC0--0x80100000 should not be used for any 254 * other needs. 255 */ 256 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 257 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 258 259 #endif /* __CONFIG_H */ 260