1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ 21 #define CONFIG_OMAP_COMMON 22 23 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 24 25 #include <asm/arch/cpu.h> /* get chip and board defs */ 26 #include <asm/arch/omap3.h> 27 28 /* 29 * Display CPU and Board information 30 */ 31 #define CONFIG_DISPLAY_CPUINFO 1 32 #define CONFIG_DISPLAY_BOARDINFO 1 33 34 /* Clock Defines */ 35 #define V_OSCK 26000000 /* Clock output from T2 */ 36 #define V_SCLK (V_OSCK >> 1) 37 38 #define CONFIG_MISC_INIT_R 39 40 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 41 #define CONFIG_SETUP_MEMORY_TAGS 1 42 #define CONFIG_INITRD_TAG 1 43 #define CONFIG_REVISION_TAG 1 44 45 /* 46 * Size of malloc() pool 47 */ 48 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 50 /* initial data */ 51 /* 52 * DDR related 53 */ 54 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 55 56 /* 57 * Hardware drivers 58 */ 59 60 /* 61 * NS16550 Configuration 62 */ 63 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 64 65 #define CONFIG_SYS_NS16550 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 69 70 /* 71 * select serial console configuration 72 */ 73 #define CONFIG_CONS_INDEX 3 74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 76 77 /* allow to overwrite serial and ethaddr */ 78 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_BAUDRATE 115200 80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 81 115200} 82 #define CONFIG_GENERIC_MMC 1 83 #define CONFIG_MMC 1 84 #define CONFIG_OMAP_HSMMC 1 85 #define CONFIG_DOS_PARTITION 1 86 87 /* 88 * USB configuration 89 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 90 * Enable CONFIG_MUSB_UDC for Device functionalities. 91 */ 92 #define CONFIG_USB_AM35X 1 93 #define CONFIG_MUSB_HCD 1 94 95 #ifdef CONFIG_USB_AM35X 96 97 #ifdef CONFIG_MUSB_HCD 98 #define CONFIG_CMD_USB 99 100 #define CONFIG_USB_STORAGE 101 #define CONGIG_CMD_STORAGE 102 #define CONFIG_CMD_FAT 103 104 #ifdef CONFIG_USB_KEYBOARD 105 #define CONFIG_SYS_USB_EVENT_POLL 106 #define CONFIG_PREBOOT "usb start" 107 #endif /* CONFIG_USB_KEYBOARD */ 108 109 #endif /* CONFIG_MUSB_HCD */ 110 111 #ifdef CONFIG_MUSB_UDC 112 /* USB device configuration */ 113 #define CONFIG_USB_DEVICE 1 114 #define CONFIG_USB_TTY 1 115 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 116 /* Change these to suit your needs */ 117 #define CONFIG_USBD_VENDORID 0x0451 118 #define CONFIG_USBD_PRODUCTID 0x5678 119 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 120 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 121 #endif /* CONFIG_MUSB_UDC */ 122 123 #endif /* CONFIG_USB_AM35X */ 124 125 /* commands to include */ 126 #include <config_cmd_default.h> 127 128 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 129 #define CONFIG_CMD_FAT /* FAT support */ 130 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 131 132 #define CONFIG_CMD_I2C /* I2C serial bus support */ 133 #define CONFIG_CMD_MMC /* MMC support */ 134 #define CONFIG_CMD_NAND /* NAND support */ 135 #define CONFIG_CMD_DHCP 136 #undef CONFIG_CMD_PING 137 138 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 139 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 140 #undef CONFIG_CMD_IMI /* iminfo */ 141 #undef CONFIG_CMD_IMLS /* List all found images */ 142 143 #define CONFIG_SYS_NO_FLASH 144 #define CONFIG_SYS_I2C 145 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 146 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 147 #define CONFIG_SYS_I2C_OMAP34XX 148 149 #undef CONFIG_CMD_NET 150 #undef CONFIG_CMD_NFS 151 /* 152 * Board NAND Info. 153 */ 154 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 155 /* to access nand */ 156 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 157 /* to access */ 158 /* nand at CS0 */ 159 160 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 161 /* NAND devices */ 162 163 #define CONFIG_JFFS2_NAND 164 /* nand device jffs2 lives on */ 165 #define CONFIG_JFFS2_DEV "nand0" 166 /* start of jffs2 partition */ 167 #define CONFIG_JFFS2_PART_OFFSET 0x680000 168 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 169 170 /* Environment information */ 171 #define CONFIG_BOOTDELAY 10 172 173 #define CONFIG_BOOTFILE "uImage" 174 175 #define CONFIG_EXTRA_ENV_SETTINGS \ 176 "loadaddr=0x82000000\0" \ 177 "console=ttyS2,115200n8\0" \ 178 "mmcdev=0\0" \ 179 "mmcargs=setenv bootargs console=${console} " \ 180 "root=/dev/mmcblk0p2 rw " \ 181 "rootfstype=ext3 rootwait\0" \ 182 "nandargs=setenv bootargs console=${console} " \ 183 "root=/dev/mtdblock4 rw " \ 184 "rootfstype=jffs2\0" \ 185 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 186 "bootscript=echo Running bootscript from mmc ...; " \ 187 "source ${loadaddr}\0" \ 188 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 189 "mmcboot=echo Booting from mmc ...; " \ 190 "run mmcargs; " \ 191 "bootm ${loadaddr}\0" \ 192 "nandboot=echo Booting from nand ...; " \ 193 "run nandargs; " \ 194 "nand read ${loadaddr} 280000 400000; " \ 195 "bootm ${loadaddr}\0" \ 196 197 #define CONFIG_BOOTCOMMAND \ 198 "mmc dev ${mmcdev}; if mmc rescan; then " \ 199 "if run loadbootscript; then " \ 200 "run bootscript; " \ 201 "else " \ 202 "if run loaduimage; then " \ 203 "run mmcboot; " \ 204 "else run nandboot; " \ 205 "fi; " \ 206 "fi; " \ 207 "else run nandboot; fi" 208 209 #define CONFIG_AUTO_COMPLETE 1 210 /* 211 * Miscellaneous configurable options 212 */ 213 #define V_PROMPT "AM3517_CRANE # " 214 215 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 216 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 217 #define CONFIG_SYS_PROMPT V_PROMPT 218 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 219 /* Print Buffer Size */ 220 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 221 sizeof(CONFIG_SYS_PROMPT) + 16) 222 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 223 /* args */ 224 /* Boot Argument Buffer Size */ 225 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 226 /* memtest works on */ 227 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 228 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 229 0x01F00000) /* 31MB */ 230 231 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 232 /* address */ 233 234 /* 235 * AM3517 has 12 GP timers, they can be driven by the system clock 236 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 237 * This rate is divided by a local divisor. 238 */ 239 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 240 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 241 242 /*----------------------------------------------------------------------- 243 * Physical Memory Map 244 */ 245 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 246 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 247 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 248 249 /*----------------------------------------------------------------------- 250 * FLASH and environment organization 251 */ 252 253 /* **** PISMO SUPPORT *** */ 254 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 255 /* on one chip */ 256 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 257 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 258 259 #define CONFIG_SYS_FLASH_BASE NAND_BASE 260 261 /* Monitor at start of flash */ 262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 263 264 #define CONFIG_NAND_OMAP_GPMC 265 #define CONFIG_ENV_IS_IN_NAND 1 266 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 267 268 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 269 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 270 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 271 272 /*----------------------------------------------------------------------- 273 * CFI FLASH driver setup 274 */ 275 /* timeout values are in ticks */ 276 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 277 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 278 279 /* Flash banks JFFS2 should use */ 280 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 281 CONFIG_SYS_MAX_NAND_DEVICE) 282 #define CONFIG_SYS_JFFS2_MEM_NAND 283 /* use flash_info[2] */ 284 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 285 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 286 287 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 288 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 289 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 290 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 291 CONFIG_SYS_INIT_RAM_SIZE - \ 292 GENERATED_GBL_DATA_SIZE) 293 294 /* Defines for SPL */ 295 #define CONFIG_SPL_FRAMEWORK 296 #define CONFIG_SPL_BOARD_INIT 297 #define CONFIG_SPL_NAND_SIMPLE 298 #define CONFIG_SPL_TEXT_BASE 0x40200800 299 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 300 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 301 302 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 303 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 304 305 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 306 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 307 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 308 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 309 310 #define CONFIG_SPL_LIBCOMMON_SUPPORT 311 #define CONFIG_SPL_LIBDISK_SUPPORT 312 #define CONFIG_SPL_I2C_SUPPORT 313 #define CONFIG_SPL_LIBGENERIC_SUPPORT 314 #define CONFIG_SPL_MMC_SUPPORT 315 #define CONFIG_SPL_FAT_SUPPORT 316 #define CONFIG_SPL_SERIAL_SUPPORT 317 #define CONFIG_SPL_NAND_SUPPORT 318 #define CONFIG_SPL_NAND_BASE 319 #define CONFIG_SPL_NAND_DRIVERS 320 #define CONFIG_SPL_NAND_ECC 321 #define CONFIG_SPL_POWER_SUPPORT 322 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 323 324 /* NAND boot config */ 325 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 326 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 327 #define CONFIG_SYS_NAND_PAGE_COUNT 64 328 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 329 #define CONFIG_SYS_NAND_OOBSIZE 64 330 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 331 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 332 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 333 10, 11, 12, 13} 334 #define CONFIG_SYS_NAND_ECCSIZE 512 335 #define CONFIG_SYS_NAND_ECCBYTES 3 336 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 337 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 338 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 339 340 /* 341 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 342 * 64 bytes before this address should be set aside for u-boot.img's 343 * header. That is 0x800FFFC0--0x80100000 should not be used for any 344 * other needs. 345 */ 346 #define CONFIG_SYS_TEXT_BASE 0x80100000 347 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 348 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 349 350 #endif /* __CONFIG_H */ 351