1 /*
2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
3  *
4  * Author: Srinath.R <srinath@mistralsolutions.com>
5  *
6  * Based on include/configs/am3517evm.h
7  *
8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 /*
17  * High Level Configuration Options
18  */
19 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
20 
21 #include <asm/arch/cpu.h>		/* get chip and board defs */
22 #include <asm/arch/omap.h>
23 
24 /* Clock Defines */
25 #define V_OSCK			26000000	/* Clock output from T2 */
26 #define V_SCLK			(V_OSCK >> 1)
27 
28 #define CONFIG_MISC_INIT_R
29 
30 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
31 #define CONFIG_SETUP_MEMORY_TAGS	1
32 #define CONFIG_INITRD_TAG		1
33 #define CONFIG_REVISION_TAG		1
34 
35 /*
36  * Size of malloc() pool
37  */
38 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
39 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
40 						/* initial data */
41 /*
42  * DDR related
43  */
44 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
45 
46 /*
47  * Hardware drivers
48  */
49 
50 /*
51  * NS16550 Configuration
52  */
53 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
54 
55 #define CONFIG_SYS_NS16550_SERIAL
56 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
57 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
58 
59 /*
60  * select serial console configuration
61  */
62 #define CONFIG_CONS_INDEX		3
63 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
64 #define CONFIG_SERIAL3			3	/* UART3 on CRANEBOARD */
65 
66 /* allow to overwrite serial and ethaddr */
67 #define CONFIG_ENV_OVERWRITE
68 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
69 					115200}
70 
71 /*
72  * USB configuration
73  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
74  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
75  */
76 #define CONFIG_USB_AM35X		1
77 #define CONFIG_USB_MUSB_HCD			1
78 
79 #ifdef CONFIG_USB_AM35X
80 
81 #ifdef CONFIG_USB_MUSB_HCD
82 
83 #ifdef CONFIG_USB_KEYBOARD
84 #define CONFIG_SYS_USB_EVENT_POLL
85 #define CONFIG_PREBOOT "usb start"
86 #endif /* CONFIG_USB_KEYBOARD */
87 
88 #endif /* CONFIG_USB_MUSB_HCD */
89 
90 #ifdef CONFIG_USB_MUSB_UDC
91 /* USB device configuration */
92 #define CONFIG_USB_DEVICE		1
93 #define CONFIG_USB_TTY			1
94 /* Change these to suit your needs */
95 #define CONFIG_USBD_VENDORID		0x0451
96 #define CONFIG_USBD_PRODUCTID		0x5678
97 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
98 #define CONFIG_USBD_PRODUCT_NAME	"AM3517CRANE"
99 #endif /* CONFIG_USB_MUSB_UDC */
100 
101 #endif /* CONFIG_USB_AM35X */
102 
103 #define CONFIG_SYS_I2C
104 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
105 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
106 #define CONFIG_SYS_I2C_OMAP34XX
107 
108 /*
109  * Board NAND Info.
110  */
111 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
112 							/* to access nand */
113 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
114 							/* to access */
115 							/* nand at CS0 */
116 
117 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
118 							/* NAND devices */
119 
120 #define CONFIG_JFFS2_NAND
121 /* nand device jffs2 lives on */
122 #define CONFIG_JFFS2_DEV		"nand0"
123 /* start of jffs2 partition */
124 #define CONFIG_JFFS2_PART_OFFSET	0x680000
125 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
126 
127 /* Environment information */
128 
129 #define CONFIG_BOOTFILE		"uImage"
130 
131 #define CONFIG_EXTRA_ENV_SETTINGS \
132 	"loadaddr=0x82000000\0" \
133 	"console=ttyS2,115200n8\0" \
134 	"mmcdev=0\0" \
135 	"mmcargs=setenv bootargs console=${console} " \
136 		"root=/dev/mmcblk0p2 rw " \
137 		"rootfstype=ext3 rootwait\0" \
138 	"nandargs=setenv bootargs console=${console} " \
139 		"root=/dev/mtdblock4 rw " \
140 		"rootfstype=jffs2\0" \
141 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
142 	"bootscript=echo Running bootscript from mmc ...; " \
143 		"source ${loadaddr}\0" \
144 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
145 	"mmcboot=echo Booting from mmc ...; " \
146 		"run mmcargs; " \
147 		"bootm ${loadaddr}\0" \
148 	"nandboot=echo Booting from nand ...; " \
149 		"run nandargs; " \
150 		"nand read ${loadaddr} 280000 400000; " \
151 		"bootm ${loadaddr}\0" \
152 
153 #define CONFIG_BOOTCOMMAND \
154 	"mmc dev ${mmcdev}; if mmc rescan; then " \
155 		"if run loadbootscript; then " \
156 			"run bootscript; " \
157 		"else " \
158 			"if run loaduimage; then " \
159 				"run mmcboot; " \
160 			"else run nandboot; " \
161 			"fi; " \
162 		"fi; " \
163 	"else run nandboot; fi"
164 
165 #define CONFIG_AUTO_COMPLETE	1
166 /*
167  * Miscellaneous configurable options
168  */
169 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
170 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
171 /* Print Buffer Size */
172 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
173 					sizeof(CONFIG_SYS_PROMPT) + 16)
174 #define CONFIG_SYS_MAXARGS		32	/* max number of command */
175 						/* args */
176 /* Boot Argument Buffer Size */
177 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
178 /* memtest works on */
179 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
180 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
181 					0x01F00000) /* 31MB */
182 
183 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
184 								/* address */
185 
186 /*
187  * AM3517 has 12 GP timers, they can be driven by the system clock
188  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
189  * This rate is divided by a local divisor.
190  */
191 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
192 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
193 
194 /*-----------------------------------------------------------------------
195  * Physical Memory Map
196  */
197 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
198 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
199 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
200 
201 /*-----------------------------------------------------------------------
202  * FLASH and environment organization
203  */
204 
205 /* **** PISMO SUPPORT *** */
206 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
207 						/* on one chip */
208 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
209 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
210 
211 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
212 
213 /* Monitor at start of flash */
214 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
215 
216 #define CONFIG_NAND_OMAP_GPMC
217 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
218 
219 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB sector */
220 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
221 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
222 
223 /*-----------------------------------------------------------------------
224  * CFI FLASH driver setup
225  */
226 /* timeout values are in ticks */
227 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
228 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
229 
230 /* Flash banks JFFS2 should use */
231 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
232 					CONFIG_SYS_MAX_NAND_DEVICE)
233 #define CONFIG_SYS_JFFS2_MEM_NAND
234 /* use flash_info[2] */
235 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
236 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
237 
238 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
239 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
240 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
241 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
242 					 CONFIG_SYS_INIT_RAM_SIZE - \
243 					 GENERATED_GBL_DATA_SIZE)
244 
245 /* Defines for SPL */
246 #define CONFIG_SPL_FRAMEWORK
247 #define CONFIG_SPL_NAND_SIMPLE
248 #define CONFIG_SPL_TEXT_BASE		0x40200800
249 #define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
250 					 CONFIG_SPL_TEXT_BASE)
251 
252 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
253 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
254 
255 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
256 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
257 
258 #define CONFIG_SPL_NAND_BASE
259 #define CONFIG_SPL_NAND_DRIVERS
260 #define CONFIG_SPL_NAND_ECC
261 #define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"
262 
263 /* NAND boot config */
264 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
265 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
266 #define CONFIG_SYS_NAND_PAGE_COUNT	64
267 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
268 #define CONFIG_SYS_NAND_OOBSIZE		64
269 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
270 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
271 #define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
272 						10, 11, 12, 13}
273 #define CONFIG_SYS_NAND_ECCSIZE		512
274 #define CONFIG_SYS_NAND_ECCBYTES	3
275 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
276 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
277 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
278 
279 /*
280  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
281  * 64 bytes before this address should be set aside for u-boot.img's
282  * header. That is 0x800FFFC0--0x80100000 should not be used for any
283  * other needs.
284  */
285 #define CONFIG_SYS_TEXT_BASE		0x80100000
286 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
287 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
288 
289 #endif /* __CONFIG_H */
290