1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ 21 /* Common ARM Erratas */ 22 #define CONFIG_ARM_ERRATA_454179 23 #define CONFIG_ARM_ERRATA_430973 24 #define CONFIG_ARM_ERRATA_621766 25 26 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 27 28 #include <asm/arch/cpu.h> /* get chip and board defs */ 29 #include <asm/arch/omap.h> 30 31 /* Clock Defines */ 32 #define V_OSCK 26000000 /* Clock output from T2 */ 33 #define V_SCLK (V_OSCK >> 1) 34 35 #define CONFIG_MISC_INIT_R 36 37 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 38 #define CONFIG_SETUP_MEMORY_TAGS 1 39 #define CONFIG_INITRD_TAG 1 40 #define CONFIG_REVISION_TAG 1 41 42 /* 43 * Size of malloc() pool 44 */ 45 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 46 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 47 /* initial data */ 48 /* 49 * DDR related 50 */ 51 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 52 53 /* 54 * Hardware drivers 55 */ 56 57 /* 58 * NS16550 Configuration 59 */ 60 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 61 62 #define CONFIG_SYS_NS16550_SERIAL 63 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 64 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 65 66 /* 67 * select serial console configuration 68 */ 69 #define CONFIG_CONS_INDEX 3 70 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 71 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 72 73 /* allow to overwrite serial and ethaddr */ 74 #define CONFIG_ENV_OVERWRITE 75 #define CONFIG_BAUDRATE 115200 76 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 77 115200} 78 #define CONFIG_GENERIC_MMC 1 79 80 /* 81 * USB configuration 82 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 83 * Enable CONFIG_USB_MUSB_UDC for Device functionalities. 84 */ 85 #define CONFIG_USB_AM35X 1 86 #define CONFIG_USB_MUSB_HCD 1 87 88 #ifdef CONFIG_USB_AM35X 89 90 #ifdef CONFIG_USB_MUSB_HCD 91 92 #define CONGIG_CMD_STORAGE 93 94 #ifdef CONFIG_USB_KEYBOARD 95 #define CONFIG_SYS_USB_EVENT_POLL 96 #define CONFIG_PREBOOT "usb start" 97 #endif /* CONFIG_USB_KEYBOARD */ 98 99 #endif /* CONFIG_USB_MUSB_HCD */ 100 101 #ifdef CONFIG_USB_MUSB_UDC 102 /* USB device configuration */ 103 #define CONFIG_USB_DEVICE 1 104 #define CONFIG_USB_TTY 1 105 /* Change these to suit your needs */ 106 #define CONFIG_USBD_VENDORID 0x0451 107 #define CONFIG_USBD_PRODUCTID 0x5678 108 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 109 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 110 #endif /* CONFIG_USB_MUSB_UDC */ 111 112 #endif /* CONFIG_USB_AM35X */ 113 114 /* commands to include */ 115 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 116 117 #define CONFIG_CMD_NAND /* NAND support */ 118 119 #define CONFIG_SYS_NO_FLASH 120 #define CONFIG_SYS_I2C 121 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 122 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 123 #define CONFIG_SYS_I2C_OMAP34XX 124 125 /* 126 * Board NAND Info. 127 */ 128 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 129 /* to access nand */ 130 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 131 /* to access */ 132 /* nand at CS0 */ 133 134 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 135 /* NAND devices */ 136 137 #define CONFIG_JFFS2_NAND 138 /* nand device jffs2 lives on */ 139 #define CONFIG_JFFS2_DEV "nand0" 140 /* start of jffs2 partition */ 141 #define CONFIG_JFFS2_PART_OFFSET 0x680000 142 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 143 144 /* Environment information */ 145 146 #define CONFIG_BOOTFILE "uImage" 147 148 #define CONFIG_EXTRA_ENV_SETTINGS \ 149 "loadaddr=0x82000000\0" \ 150 "console=ttyS2,115200n8\0" \ 151 "mmcdev=0\0" \ 152 "mmcargs=setenv bootargs console=${console} " \ 153 "root=/dev/mmcblk0p2 rw " \ 154 "rootfstype=ext3 rootwait\0" \ 155 "nandargs=setenv bootargs console=${console} " \ 156 "root=/dev/mtdblock4 rw " \ 157 "rootfstype=jffs2\0" \ 158 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 159 "bootscript=echo Running bootscript from mmc ...; " \ 160 "source ${loadaddr}\0" \ 161 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 162 "mmcboot=echo Booting from mmc ...; " \ 163 "run mmcargs; " \ 164 "bootm ${loadaddr}\0" \ 165 "nandboot=echo Booting from nand ...; " \ 166 "run nandargs; " \ 167 "nand read ${loadaddr} 280000 400000; " \ 168 "bootm ${loadaddr}\0" \ 169 170 #define CONFIG_BOOTCOMMAND \ 171 "mmc dev ${mmcdev}; if mmc rescan; then " \ 172 "if run loadbootscript; then " \ 173 "run bootscript; " \ 174 "else " \ 175 "if run loaduimage; then " \ 176 "run mmcboot; " \ 177 "else run nandboot; " \ 178 "fi; " \ 179 "fi; " \ 180 "else run nandboot; fi" 181 182 #define CONFIG_AUTO_COMPLETE 1 183 /* 184 * Miscellaneous configurable options 185 */ 186 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 187 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 188 /* Print Buffer Size */ 189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 190 sizeof(CONFIG_SYS_PROMPT) + 16) 191 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 192 /* args */ 193 /* Boot Argument Buffer Size */ 194 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 195 /* memtest works on */ 196 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 197 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 198 0x01F00000) /* 31MB */ 199 200 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 201 /* address */ 202 203 /* 204 * AM3517 has 12 GP timers, they can be driven by the system clock 205 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 206 * This rate is divided by a local divisor. 207 */ 208 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 209 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 210 211 /*----------------------------------------------------------------------- 212 * Physical Memory Map 213 */ 214 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 215 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 216 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 217 218 /*----------------------------------------------------------------------- 219 * FLASH and environment organization 220 */ 221 222 /* **** PISMO SUPPORT *** */ 223 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 224 /* on one chip */ 225 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 226 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 227 228 #define CONFIG_SYS_FLASH_BASE NAND_BASE 229 230 /* Monitor at start of flash */ 231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 232 233 #define CONFIG_NAND_OMAP_GPMC 234 #define CONFIG_ENV_IS_IN_NAND 1 235 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 236 237 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 238 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 239 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 240 241 /*----------------------------------------------------------------------- 242 * CFI FLASH driver setup 243 */ 244 /* timeout values are in ticks */ 245 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 246 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 247 248 /* Flash banks JFFS2 should use */ 249 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 250 CONFIG_SYS_MAX_NAND_DEVICE) 251 #define CONFIG_SYS_JFFS2_MEM_NAND 252 /* use flash_info[2] */ 253 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 254 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 255 256 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 257 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 258 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 259 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 260 CONFIG_SYS_INIT_RAM_SIZE - \ 261 GENERATED_GBL_DATA_SIZE) 262 263 /* Defines for SPL */ 264 #define CONFIG_SPL_FRAMEWORK 265 #define CONFIG_SPL_BOARD_INIT 266 #define CONFIG_SPL_NAND_SIMPLE 267 #define CONFIG_SPL_TEXT_BASE 0x40200800 268 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 269 CONFIG_SPL_TEXT_BASE) 270 271 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 272 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 273 274 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 275 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 276 277 #define CONFIG_SPL_NAND_BASE 278 #define CONFIG_SPL_NAND_DRIVERS 279 #define CONFIG_SPL_NAND_ECC 280 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 281 282 /* NAND boot config */ 283 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 284 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 285 #define CONFIG_SYS_NAND_PAGE_COUNT 64 286 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 287 #define CONFIG_SYS_NAND_OOBSIZE 64 288 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 289 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 290 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 291 10, 11, 12, 13} 292 #define CONFIG_SYS_NAND_ECCSIZE 512 293 #define CONFIG_SYS_NAND_ECCBYTES 3 294 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 295 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 296 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 297 298 /* 299 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 300 * 64 bytes before this address should be set aside for u-boot.img's 301 * header. That is 0x800FFFC0--0x80100000 should not be used for any 302 * other needs. 303 */ 304 #define CONFIG_SYS_TEXT_BASE 0x80100000 305 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 306 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 307 308 #endif /* __CONFIG_H */ 309