1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 20 21 #include <asm/arch/cpu.h> /* get chip and board defs */ 22 #include <asm/arch/omap.h> 23 24 /* Clock Defines */ 25 #define V_OSCK 26000000 /* Clock output from T2 */ 26 #define V_SCLK (V_OSCK >> 1) 27 28 #define CONFIG_MISC_INIT_R 29 30 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 31 #define CONFIG_SETUP_MEMORY_TAGS 1 32 #define CONFIG_INITRD_TAG 1 33 #define CONFIG_REVISION_TAG 1 34 35 /* 36 * Size of malloc() pool 37 */ 38 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 40 /* initial data */ 41 /* 42 * DDR related 43 */ 44 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 45 46 /* 47 * Hardware drivers 48 */ 49 50 /* 51 * NS16550 Configuration 52 */ 53 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 54 55 #define CONFIG_SYS_NS16550_SERIAL 56 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 57 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 58 59 /* 60 * select serial console configuration 61 */ 62 #define CONFIG_CONS_INDEX 3 63 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 64 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 65 66 /* allow to overwrite serial and ethaddr */ 67 #define CONFIG_ENV_OVERWRITE 68 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 69 115200} 70 71 /* 72 * USB configuration 73 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 74 * Enable CONFIG_USB_MUSB_UDC for Device functionalities. 75 */ 76 #define CONFIG_USB_AM35X 1 77 #define CONFIG_USB_MUSB_HCD 1 78 79 #ifdef CONFIG_USB_AM35X 80 81 #ifdef CONFIG_USB_MUSB_HCD 82 83 #ifdef CONFIG_USB_KEYBOARD 84 #define CONFIG_SYS_USB_EVENT_POLL 85 #define CONFIG_PREBOOT "usb start" 86 #endif /* CONFIG_USB_KEYBOARD */ 87 88 #endif /* CONFIG_USB_MUSB_HCD */ 89 90 #ifdef CONFIG_USB_MUSB_UDC 91 /* USB device configuration */ 92 #define CONFIG_USB_DEVICE 1 93 #define CONFIG_USB_TTY 1 94 /* Change these to suit your needs */ 95 #define CONFIG_USBD_VENDORID 0x0451 96 #define CONFIG_USBD_PRODUCTID 0x5678 97 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 98 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 99 #endif /* CONFIG_USB_MUSB_UDC */ 100 101 #endif /* CONFIG_USB_AM35X */ 102 103 /* commands to include */ 104 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 105 106 #define CONFIG_CMD_NAND /* NAND support */ 107 108 #define CONFIG_SYS_I2C 109 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 110 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 111 #define CONFIG_SYS_I2C_OMAP34XX 112 113 /* 114 * Board NAND Info. 115 */ 116 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 117 /* to access nand */ 118 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 119 /* to access */ 120 /* nand at CS0 */ 121 122 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 123 /* NAND devices */ 124 125 #define CONFIG_JFFS2_NAND 126 /* nand device jffs2 lives on */ 127 #define CONFIG_JFFS2_DEV "nand0" 128 /* start of jffs2 partition */ 129 #define CONFIG_JFFS2_PART_OFFSET 0x680000 130 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 131 132 /* Environment information */ 133 134 #define CONFIG_BOOTFILE "uImage" 135 136 #define CONFIG_EXTRA_ENV_SETTINGS \ 137 "loadaddr=0x82000000\0" \ 138 "console=ttyS2,115200n8\0" \ 139 "mmcdev=0\0" \ 140 "mmcargs=setenv bootargs console=${console} " \ 141 "root=/dev/mmcblk0p2 rw " \ 142 "rootfstype=ext3 rootwait\0" \ 143 "nandargs=setenv bootargs console=${console} " \ 144 "root=/dev/mtdblock4 rw " \ 145 "rootfstype=jffs2\0" \ 146 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 147 "bootscript=echo Running bootscript from mmc ...; " \ 148 "source ${loadaddr}\0" \ 149 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 150 "mmcboot=echo Booting from mmc ...; " \ 151 "run mmcargs; " \ 152 "bootm ${loadaddr}\0" \ 153 "nandboot=echo Booting from nand ...; " \ 154 "run nandargs; " \ 155 "nand read ${loadaddr} 280000 400000; " \ 156 "bootm ${loadaddr}\0" \ 157 158 #define CONFIG_BOOTCOMMAND \ 159 "mmc dev ${mmcdev}; if mmc rescan; then " \ 160 "if run loadbootscript; then " \ 161 "run bootscript; " \ 162 "else " \ 163 "if run loaduimage; then " \ 164 "run mmcboot; " \ 165 "else run nandboot; " \ 166 "fi; " \ 167 "fi; " \ 168 "else run nandboot; fi" 169 170 #define CONFIG_AUTO_COMPLETE 1 171 /* 172 * Miscellaneous configurable options 173 */ 174 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 175 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 176 /* Print Buffer Size */ 177 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 178 sizeof(CONFIG_SYS_PROMPT) + 16) 179 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 180 /* args */ 181 /* Boot Argument Buffer Size */ 182 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 183 /* memtest works on */ 184 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 185 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 186 0x01F00000) /* 31MB */ 187 188 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 189 /* address */ 190 191 /* 192 * AM3517 has 12 GP timers, they can be driven by the system clock 193 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 194 * This rate is divided by a local divisor. 195 */ 196 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 197 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 198 199 /*----------------------------------------------------------------------- 200 * Physical Memory Map 201 */ 202 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 203 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 204 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 205 206 /*----------------------------------------------------------------------- 207 * FLASH and environment organization 208 */ 209 210 /* **** PISMO SUPPORT *** */ 211 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 212 /* on one chip */ 213 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 214 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 215 216 #define CONFIG_SYS_FLASH_BASE NAND_BASE 217 218 /* Monitor at start of flash */ 219 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 220 221 #define CONFIG_NAND_OMAP_GPMC 222 #define CONFIG_ENV_IS_IN_NAND 1 223 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 224 225 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 226 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 227 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 228 229 /*----------------------------------------------------------------------- 230 * CFI FLASH driver setup 231 */ 232 /* timeout values are in ticks */ 233 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 234 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 235 236 /* Flash banks JFFS2 should use */ 237 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 238 CONFIG_SYS_MAX_NAND_DEVICE) 239 #define CONFIG_SYS_JFFS2_MEM_NAND 240 /* use flash_info[2] */ 241 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 242 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 243 244 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 245 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 246 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 247 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 248 CONFIG_SYS_INIT_RAM_SIZE - \ 249 GENERATED_GBL_DATA_SIZE) 250 251 /* Defines for SPL */ 252 #define CONFIG_SPL_FRAMEWORK 253 #define CONFIG_SPL_BOARD_INIT 254 #define CONFIG_SPL_NAND_SIMPLE 255 #define CONFIG_SPL_TEXT_BASE 0x40200800 256 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 257 CONFIG_SPL_TEXT_BASE) 258 259 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 260 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 261 262 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 263 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 264 265 #define CONFIG_SPL_NAND_BASE 266 #define CONFIG_SPL_NAND_DRIVERS 267 #define CONFIG_SPL_NAND_ECC 268 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 269 270 /* NAND boot config */ 271 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 272 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 273 #define CONFIG_SYS_NAND_PAGE_COUNT 64 274 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 275 #define CONFIG_SYS_NAND_OOBSIZE 64 276 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 277 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 278 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 279 10, 11, 12, 13} 280 #define CONFIG_SYS_NAND_ECCSIZE 512 281 #define CONFIG_SYS_NAND_ECCBYTES 3 282 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 283 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 284 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 285 286 /* 287 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 288 * 64 bytes before this address should be set aside for u-boot.img's 289 * header. That is 0x800FFFC0--0x80100000 should not be used for any 290 * other needs. 291 */ 292 #define CONFIG_SYS_TEXT_BASE 0x80100000 293 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 294 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 295 296 #endif /* __CONFIG_H */ 297