1 /*
2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
3  *
4  * Author: Srinath.R <srinath@mistralsolutions.com>
5  *
6  * Based on include/configs/am3517evm.h
7  *
8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 #define CONFIG_SYS_CACHELINE_SIZE	64
17 
18 /*
19  * High Level Configuration Options
20  */
21 #define CONFIG_OMAP		1	/* in a TI OMAP core */
22 #define CONFIG_OMAP3_AM3517CRANE	1	/* working with CRANEBOARD */
23 #define CONFIG_OMAP_COMMON
24 /* Common ARM Erratas */
25 #define CONFIG_ARM_ERRATA_454179
26 #define CONFIG_ARM_ERRATA_430973
27 #define CONFIG_ARM_ERRATA_621766
28 
29 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
30 
31 #include <asm/arch/cpu.h>		/* get chip and board defs */
32 #include <asm/arch/omap.h>
33 
34 /*
35  * Display CPU and Board information
36  */
37 #define CONFIG_DISPLAY_CPUINFO		1
38 #define CONFIG_DISPLAY_BOARDINFO	1
39 
40 /* Clock Defines */
41 #define V_OSCK			26000000	/* Clock output from T2 */
42 #define V_SCLK			(V_OSCK >> 1)
43 
44 #define CONFIG_MISC_INIT_R
45 
46 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
47 #define CONFIG_SETUP_MEMORY_TAGS	1
48 #define CONFIG_INITRD_TAG		1
49 #define CONFIG_REVISION_TAG		1
50 
51 /*
52  * Size of malloc() pool
53  */
54 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
55 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
56 						/* initial data */
57 /*
58  * DDR related
59  */
60 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
61 
62 /*
63  * Hardware drivers
64  */
65 
66 /*
67  * NS16550 Configuration
68  */
69 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
70 
71 #define CONFIG_SYS_NS16550_SERIAL
72 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
73 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
74 
75 /*
76  * select serial console configuration
77  */
78 #define CONFIG_CONS_INDEX		3
79 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
80 #define CONFIG_SERIAL3			3	/* UART3 on CRANEBOARD */
81 
82 /* allow to overwrite serial and ethaddr */
83 #define CONFIG_ENV_OVERWRITE
84 #define CONFIG_BAUDRATE			115200
85 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
86 					115200}
87 #define CONFIG_GENERIC_MMC		1
88 #define CONFIG_MMC			1
89 #define CONFIG_OMAP_HSMMC		1
90 #define CONFIG_DOS_PARTITION		1
91 
92 /*
93  * USB configuration
94  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
95  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
96  */
97 #define CONFIG_USB_AM35X		1
98 #define CONFIG_USB_MUSB_HCD			1
99 
100 #ifdef CONFIG_USB_AM35X
101 
102 #ifdef CONFIG_USB_MUSB_HCD
103 #define CONFIG_CMD_USB
104 
105 #define CONFIG_USB_STORAGE
106 #define CONGIG_CMD_STORAGE
107 #define CONFIG_CMD_FAT
108 
109 #ifdef CONFIG_USB_KEYBOARD
110 #define CONFIG_SYS_USB_EVENT_POLL
111 #define CONFIG_PREBOOT "usb start"
112 #endif /* CONFIG_USB_KEYBOARD */
113 
114 #endif /* CONFIG_USB_MUSB_HCD */
115 
116 #ifdef CONFIG_USB_MUSB_UDC
117 /* USB device configuration */
118 #define CONFIG_USB_DEVICE		1
119 #define CONFIG_USB_TTY			1
120 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
121 /* Change these to suit your needs */
122 #define CONFIG_USBD_VENDORID		0x0451
123 #define CONFIG_USBD_PRODUCTID		0x5678
124 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
125 #define CONFIG_USBD_PRODUCT_NAME	"AM3517CRANE"
126 #endif /* CONFIG_USB_MUSB_UDC */
127 
128 #endif /* CONFIG_USB_AM35X */
129 
130 /* commands to include */
131 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
132 #define CONFIG_CMD_FAT		/* FAT support			*/
133 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
134 
135 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
136 #define CONFIG_CMD_MMC		/* MMC support			*/
137 #define CONFIG_CMD_NAND		/* NAND support			*/
138 #define CONFIG_CMD_DHCP
139 #undef CONFIG_CMD_PING
140 
141 
142 #define CONFIG_SYS_NO_FLASH
143 #define CONFIG_SYS_I2C
144 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
145 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
146 #define CONFIG_SYS_I2C_OMAP34XX
147 
148 /*
149  * Board NAND Info.
150  */
151 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
152 							/* to access nand */
153 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
154 							/* to access */
155 							/* nand at CS0 */
156 
157 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
158 							/* NAND devices */
159 
160 #define CONFIG_JFFS2_NAND
161 /* nand device jffs2 lives on */
162 #define CONFIG_JFFS2_DEV		"nand0"
163 /* start of jffs2 partition */
164 #define CONFIG_JFFS2_PART_OFFSET	0x680000
165 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
166 
167 /* Environment information */
168 #define CONFIG_BOOTDELAY	10
169 
170 #define CONFIG_BOOTFILE		"uImage"
171 
172 #define CONFIG_EXTRA_ENV_SETTINGS \
173 	"loadaddr=0x82000000\0" \
174 	"console=ttyS2,115200n8\0" \
175 	"mmcdev=0\0" \
176 	"mmcargs=setenv bootargs console=${console} " \
177 		"root=/dev/mmcblk0p2 rw " \
178 		"rootfstype=ext3 rootwait\0" \
179 	"nandargs=setenv bootargs console=${console} " \
180 		"root=/dev/mtdblock4 rw " \
181 		"rootfstype=jffs2\0" \
182 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
183 	"bootscript=echo Running bootscript from mmc ...; " \
184 		"source ${loadaddr}\0" \
185 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
186 	"mmcboot=echo Booting from mmc ...; " \
187 		"run mmcargs; " \
188 		"bootm ${loadaddr}\0" \
189 	"nandboot=echo Booting from nand ...; " \
190 		"run nandargs; " \
191 		"nand read ${loadaddr} 280000 400000; " \
192 		"bootm ${loadaddr}\0" \
193 
194 #define CONFIG_BOOTCOMMAND \
195 	"mmc dev ${mmcdev}; if mmc rescan; then " \
196 		"if run loadbootscript; then " \
197 			"run bootscript; " \
198 		"else " \
199 			"if run loaduimage; then " \
200 				"run mmcboot; " \
201 			"else run nandboot; " \
202 			"fi; " \
203 		"fi; " \
204 	"else run nandboot; fi"
205 
206 #define CONFIG_AUTO_COMPLETE	1
207 /*
208  * Miscellaneous configurable options
209  */
210 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
211 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
212 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
213 /* Print Buffer Size */
214 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
215 					sizeof(CONFIG_SYS_PROMPT) + 16)
216 #define CONFIG_SYS_MAXARGS		32	/* max number of command */
217 						/* args */
218 /* Boot Argument Buffer Size */
219 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
220 /* memtest works on */
221 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
222 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
223 					0x01F00000) /* 31MB */
224 
225 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
226 								/* address */
227 
228 /*
229  * AM3517 has 12 GP timers, they can be driven by the system clock
230  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
231  * This rate is divided by a local divisor.
232  */
233 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
234 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
235 
236 /*-----------------------------------------------------------------------
237  * Physical Memory Map
238  */
239 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
240 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
241 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
242 
243 /*-----------------------------------------------------------------------
244  * FLASH and environment organization
245  */
246 
247 /* **** PISMO SUPPORT *** */
248 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
249 						/* on one chip */
250 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
251 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
252 
253 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
254 
255 /* Monitor at start of flash */
256 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
257 
258 #define CONFIG_NAND_OMAP_GPMC
259 #define CONFIG_ENV_IS_IN_NAND		1
260 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
261 
262 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB sector */
263 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
264 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
265 
266 /*-----------------------------------------------------------------------
267  * CFI FLASH driver setup
268  */
269 /* timeout values are in ticks */
270 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
271 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
272 
273 /* Flash banks JFFS2 should use */
274 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
275 					CONFIG_SYS_MAX_NAND_DEVICE)
276 #define CONFIG_SYS_JFFS2_MEM_NAND
277 /* use flash_info[2] */
278 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
279 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
280 
281 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
282 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
283 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
284 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
285 					 CONFIG_SYS_INIT_RAM_SIZE - \
286 					 GENERATED_GBL_DATA_SIZE)
287 
288 /* Defines for SPL */
289 #define CONFIG_SPL_FRAMEWORK
290 #define CONFIG_SPL_BOARD_INIT
291 #define CONFIG_SPL_NAND_SIMPLE
292 #define CONFIG_SPL_TEXT_BASE		0x40200800
293 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
294 
295 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
296 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
297 
298 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
299 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
300 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
301 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
302 
303 #define CONFIG_SPL_LIBCOMMON_SUPPORT
304 #define CONFIG_SPL_LIBDISK_SUPPORT
305 #define CONFIG_SPL_I2C_SUPPORT
306 #define CONFIG_SPL_LIBGENERIC_SUPPORT
307 #define CONFIG_SPL_MMC_SUPPORT
308 #define CONFIG_SPL_FAT_SUPPORT
309 #define CONFIG_SPL_SERIAL_SUPPORT
310 #define CONFIG_SPL_NAND_SUPPORT
311 #define CONFIG_SPL_NAND_BASE
312 #define CONFIG_SPL_NAND_DRIVERS
313 #define CONFIG_SPL_NAND_ECC
314 #define CONFIG_SPL_POWER_SUPPORT
315 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
316 
317 /* NAND boot config */
318 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
319 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
320 #define CONFIG_SYS_NAND_PAGE_COUNT	64
321 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
322 #define CONFIG_SYS_NAND_OOBSIZE		64
323 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
324 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
325 #define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
326 						10, 11, 12, 13}
327 #define CONFIG_SYS_NAND_ECCSIZE		512
328 #define CONFIG_SYS_NAND_ECCBYTES	3
329 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
330 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
331 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
332 
333 /*
334  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
335  * 64 bytes before this address should be set aside for u-boot.img's
336  * header. That is 0x800FFFC0--0x80100000 should not be used for any
337  * other needs.
338  */
339 #define CONFIG_SYS_TEXT_BASE		0x80100000
340 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
341 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
342 
343 #endif /* __CONFIG_H */
344