1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ 21 #define CONFIG_OMAP_COMMON 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 28 29 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/omap.h> 31 32 /* 33 * Display CPU and Board information 34 */ 35 #define CONFIG_DISPLAY_CPUINFO 1 36 #define CONFIG_DISPLAY_BOARDINFO 1 37 38 /* Clock Defines */ 39 #define V_OSCK 26000000 /* Clock output from T2 */ 40 #define V_SCLK (V_OSCK >> 1) 41 42 #define CONFIG_MISC_INIT_R 43 44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 45 #define CONFIG_SETUP_MEMORY_TAGS 1 46 #define CONFIG_INITRD_TAG 1 47 #define CONFIG_REVISION_TAG 1 48 49 /* 50 * Size of malloc() pool 51 */ 52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 53 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 54 /* initial data */ 55 /* 56 * DDR related 57 */ 58 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 59 60 /* 61 * Hardware drivers 62 */ 63 64 /* 65 * NS16550 Configuration 66 */ 67 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 68 69 #define CONFIG_SYS_NS16550 70 #define CONFIG_SYS_NS16550_SERIAL 71 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 72 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 73 74 /* 75 * select serial console configuration 76 */ 77 #define CONFIG_CONS_INDEX 3 78 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 79 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 80 81 /* allow to overwrite serial and ethaddr */ 82 #define CONFIG_ENV_OVERWRITE 83 #define CONFIG_BAUDRATE 115200 84 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 85 115200} 86 #define CONFIG_GENERIC_MMC 1 87 #define CONFIG_MMC 1 88 #define CONFIG_OMAP_HSMMC 1 89 #define CONFIG_DOS_PARTITION 1 90 91 /* 92 * USB configuration 93 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 94 * Enable CONFIG_MUSB_UDC for Device functionalities. 95 */ 96 #define CONFIG_USB_AM35X 1 97 #define CONFIG_MUSB_HCD 1 98 99 #ifdef CONFIG_USB_AM35X 100 101 #ifdef CONFIG_MUSB_HCD 102 #define CONFIG_CMD_USB 103 104 #define CONFIG_USB_STORAGE 105 #define CONGIG_CMD_STORAGE 106 #define CONFIG_CMD_FAT 107 108 #ifdef CONFIG_USB_KEYBOARD 109 #define CONFIG_SYS_USB_EVENT_POLL 110 #define CONFIG_PREBOOT "usb start" 111 #endif /* CONFIG_USB_KEYBOARD */ 112 113 #endif /* CONFIG_MUSB_HCD */ 114 115 #ifdef CONFIG_MUSB_UDC 116 /* USB device configuration */ 117 #define CONFIG_USB_DEVICE 1 118 #define CONFIG_USB_TTY 1 119 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 120 /* Change these to suit your needs */ 121 #define CONFIG_USBD_VENDORID 0x0451 122 #define CONFIG_USBD_PRODUCTID 0x5678 123 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 124 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 125 #endif /* CONFIG_MUSB_UDC */ 126 127 #endif /* CONFIG_USB_AM35X */ 128 129 /* commands to include */ 130 #include <config_cmd_default.h> 131 132 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 133 #define CONFIG_CMD_FAT /* FAT support */ 134 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 135 136 #define CONFIG_CMD_I2C /* I2C serial bus support */ 137 #define CONFIG_CMD_MMC /* MMC support */ 138 #define CONFIG_CMD_NAND /* NAND support */ 139 #define CONFIG_CMD_DHCP 140 #undef CONFIG_CMD_PING 141 142 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 143 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 144 #undef CONFIG_CMD_IMI /* iminfo */ 145 #undef CONFIG_CMD_IMLS /* List all found images */ 146 147 #define CONFIG_SYS_NO_FLASH 148 #define CONFIG_SYS_I2C 149 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 150 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 151 #define CONFIG_SYS_I2C_OMAP34XX 152 153 #undef CONFIG_CMD_NFS 154 /* 155 * Board NAND Info. 156 */ 157 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 158 /* to access nand */ 159 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 160 /* to access */ 161 /* nand at CS0 */ 162 163 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 164 /* NAND devices */ 165 166 #define CONFIG_JFFS2_NAND 167 /* nand device jffs2 lives on */ 168 #define CONFIG_JFFS2_DEV "nand0" 169 /* start of jffs2 partition */ 170 #define CONFIG_JFFS2_PART_OFFSET 0x680000 171 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 172 173 /* Environment information */ 174 #define CONFIG_BOOTDELAY 10 175 176 #define CONFIG_BOOTFILE "uImage" 177 178 #define CONFIG_EXTRA_ENV_SETTINGS \ 179 "loadaddr=0x82000000\0" \ 180 "console=ttyS2,115200n8\0" \ 181 "mmcdev=0\0" \ 182 "mmcargs=setenv bootargs console=${console} " \ 183 "root=/dev/mmcblk0p2 rw " \ 184 "rootfstype=ext3 rootwait\0" \ 185 "nandargs=setenv bootargs console=${console} " \ 186 "root=/dev/mtdblock4 rw " \ 187 "rootfstype=jffs2\0" \ 188 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 189 "bootscript=echo Running bootscript from mmc ...; " \ 190 "source ${loadaddr}\0" \ 191 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 192 "mmcboot=echo Booting from mmc ...; " \ 193 "run mmcargs; " \ 194 "bootm ${loadaddr}\0" \ 195 "nandboot=echo Booting from nand ...; " \ 196 "run nandargs; " \ 197 "nand read ${loadaddr} 280000 400000; " \ 198 "bootm ${loadaddr}\0" \ 199 200 #define CONFIG_BOOTCOMMAND \ 201 "mmc dev ${mmcdev}; if mmc rescan; then " \ 202 "if run loadbootscript; then " \ 203 "run bootscript; " \ 204 "else " \ 205 "if run loaduimage; then " \ 206 "run mmcboot; " \ 207 "else run nandboot; " \ 208 "fi; " \ 209 "fi; " \ 210 "else run nandboot; fi" 211 212 #define CONFIG_AUTO_COMPLETE 1 213 /* 214 * Miscellaneous configurable options 215 */ 216 #define V_PROMPT "AM3517_CRANE # " 217 218 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 219 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 220 #define CONFIG_SYS_PROMPT V_PROMPT 221 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 222 /* Print Buffer Size */ 223 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 224 sizeof(CONFIG_SYS_PROMPT) + 16) 225 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 226 /* args */ 227 /* Boot Argument Buffer Size */ 228 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 229 /* memtest works on */ 230 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 231 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 232 0x01F00000) /* 31MB */ 233 234 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 235 /* address */ 236 237 /* 238 * AM3517 has 12 GP timers, they can be driven by the system clock 239 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 240 * This rate is divided by a local divisor. 241 */ 242 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 243 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 244 245 /*----------------------------------------------------------------------- 246 * Physical Memory Map 247 */ 248 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 249 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 250 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 251 252 /*----------------------------------------------------------------------- 253 * FLASH and environment organization 254 */ 255 256 /* **** PISMO SUPPORT *** */ 257 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 258 /* on one chip */ 259 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 260 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 261 262 #define CONFIG_SYS_FLASH_BASE NAND_BASE 263 264 /* Monitor at start of flash */ 265 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 266 267 #define CONFIG_NAND_OMAP_GPMC 268 #define CONFIG_ENV_IS_IN_NAND 1 269 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 270 271 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 272 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 273 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 274 275 /*----------------------------------------------------------------------- 276 * CFI FLASH driver setup 277 */ 278 /* timeout values are in ticks */ 279 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 280 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 281 282 /* Flash banks JFFS2 should use */ 283 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 284 CONFIG_SYS_MAX_NAND_DEVICE) 285 #define CONFIG_SYS_JFFS2_MEM_NAND 286 /* use flash_info[2] */ 287 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 288 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 289 290 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 291 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 292 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 293 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 294 CONFIG_SYS_INIT_RAM_SIZE - \ 295 GENERATED_GBL_DATA_SIZE) 296 297 /* Defines for SPL */ 298 #define CONFIG_SPL_FRAMEWORK 299 #define CONFIG_SPL_BOARD_INIT 300 #define CONFIG_SPL_NAND_SIMPLE 301 #define CONFIG_SPL_TEXT_BASE 0x40200800 302 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 303 304 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 305 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 306 307 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 308 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 309 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 310 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 311 312 #define CONFIG_SPL_LIBCOMMON_SUPPORT 313 #define CONFIG_SPL_LIBDISK_SUPPORT 314 #define CONFIG_SPL_I2C_SUPPORT 315 #define CONFIG_SPL_LIBGENERIC_SUPPORT 316 #define CONFIG_SPL_MMC_SUPPORT 317 #define CONFIG_SPL_FAT_SUPPORT 318 #define CONFIG_SPL_SERIAL_SUPPORT 319 #define CONFIG_SPL_NAND_SUPPORT 320 #define CONFIG_SPL_NAND_BASE 321 #define CONFIG_SPL_NAND_DRIVERS 322 #define CONFIG_SPL_NAND_ECC 323 #define CONFIG_SPL_POWER_SUPPORT 324 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 325 326 /* NAND boot config */ 327 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 328 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 329 #define CONFIG_SYS_NAND_PAGE_COUNT 64 330 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 331 #define CONFIG_SYS_NAND_OOBSIZE 64 332 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 333 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 334 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 335 10, 11, 12, 13} 336 #define CONFIG_SYS_NAND_ECCSIZE 512 337 #define CONFIG_SYS_NAND_ECCBYTES 3 338 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 339 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 340 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 341 342 /* 343 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 344 * 64 bytes before this address should be set aside for u-boot.img's 345 * header. That is 0x800FFFC0--0x80100000 should not be used for any 346 * other needs. 347 */ 348 #define CONFIG_SYS_TEXT_BASE 0x80100000 349 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 350 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 351 352 #endif /* __CONFIG_H */ 353