1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ 21 22 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 23 24 #include <asm/arch/cpu.h> /* get chip and board defs */ 25 #include <asm/arch/omap.h> 26 27 /* Clock Defines */ 28 #define V_OSCK 26000000 /* Clock output from T2 */ 29 #define V_SCLK (V_OSCK >> 1) 30 31 #define CONFIG_MISC_INIT_R 32 33 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 34 #define CONFIG_SETUP_MEMORY_TAGS 1 35 #define CONFIG_INITRD_TAG 1 36 #define CONFIG_REVISION_TAG 1 37 38 /* 39 * Size of malloc() pool 40 */ 41 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 43 /* initial data */ 44 /* 45 * DDR related 46 */ 47 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 48 49 /* 50 * Hardware drivers 51 */ 52 53 /* 54 * NS16550 Configuration 55 */ 56 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 57 58 #define CONFIG_SYS_NS16550_SERIAL 59 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 60 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 61 62 /* 63 * select serial console configuration 64 */ 65 #define CONFIG_CONS_INDEX 3 66 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 67 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 68 69 /* allow to overwrite serial and ethaddr */ 70 #define CONFIG_ENV_OVERWRITE 71 #define CONFIG_BAUDRATE 115200 72 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 73 115200} 74 75 /* 76 * USB configuration 77 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 78 * Enable CONFIG_USB_MUSB_UDC for Device functionalities. 79 */ 80 #define CONFIG_USB_AM35X 1 81 #define CONFIG_USB_MUSB_HCD 1 82 83 #ifdef CONFIG_USB_AM35X 84 85 #ifdef CONFIG_USB_MUSB_HCD 86 87 #ifdef CONFIG_USB_KEYBOARD 88 #define CONFIG_SYS_USB_EVENT_POLL 89 #define CONFIG_PREBOOT "usb start" 90 #endif /* CONFIG_USB_KEYBOARD */ 91 92 #endif /* CONFIG_USB_MUSB_HCD */ 93 94 #ifdef CONFIG_USB_MUSB_UDC 95 /* USB device configuration */ 96 #define CONFIG_USB_DEVICE 1 97 #define CONFIG_USB_TTY 1 98 /* Change these to suit your needs */ 99 #define CONFIG_USBD_VENDORID 0x0451 100 #define CONFIG_USBD_PRODUCTID 0x5678 101 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 102 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 103 #endif /* CONFIG_USB_MUSB_UDC */ 104 105 #endif /* CONFIG_USB_AM35X */ 106 107 /* commands to include */ 108 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 109 110 #define CONFIG_CMD_NAND /* NAND support */ 111 112 #define CONFIG_SYS_I2C 113 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 114 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 115 #define CONFIG_SYS_I2C_OMAP34XX 116 117 /* 118 * Board NAND Info. 119 */ 120 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 121 /* to access nand */ 122 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 123 /* to access */ 124 /* nand at CS0 */ 125 126 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 127 /* NAND devices */ 128 129 #define CONFIG_JFFS2_NAND 130 /* nand device jffs2 lives on */ 131 #define CONFIG_JFFS2_DEV "nand0" 132 /* start of jffs2 partition */ 133 #define CONFIG_JFFS2_PART_OFFSET 0x680000 134 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 135 136 /* Environment information */ 137 138 #define CONFIG_BOOTFILE "uImage" 139 140 #define CONFIG_EXTRA_ENV_SETTINGS \ 141 "loadaddr=0x82000000\0" \ 142 "console=ttyS2,115200n8\0" \ 143 "mmcdev=0\0" \ 144 "mmcargs=setenv bootargs console=${console} " \ 145 "root=/dev/mmcblk0p2 rw " \ 146 "rootfstype=ext3 rootwait\0" \ 147 "nandargs=setenv bootargs console=${console} " \ 148 "root=/dev/mtdblock4 rw " \ 149 "rootfstype=jffs2\0" \ 150 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 151 "bootscript=echo Running bootscript from mmc ...; " \ 152 "source ${loadaddr}\0" \ 153 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 154 "mmcboot=echo Booting from mmc ...; " \ 155 "run mmcargs; " \ 156 "bootm ${loadaddr}\0" \ 157 "nandboot=echo Booting from nand ...; " \ 158 "run nandargs; " \ 159 "nand read ${loadaddr} 280000 400000; " \ 160 "bootm ${loadaddr}\0" \ 161 162 #define CONFIG_BOOTCOMMAND \ 163 "mmc dev ${mmcdev}; if mmc rescan; then " \ 164 "if run loadbootscript; then " \ 165 "run bootscript; " \ 166 "else " \ 167 "if run loaduimage; then " \ 168 "run mmcboot; " \ 169 "else run nandboot; " \ 170 "fi; " \ 171 "fi; " \ 172 "else run nandboot; fi" 173 174 #define CONFIG_AUTO_COMPLETE 1 175 /* 176 * Miscellaneous configurable options 177 */ 178 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 179 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 180 /* Print Buffer Size */ 181 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 182 sizeof(CONFIG_SYS_PROMPT) + 16) 183 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 184 /* args */ 185 /* Boot Argument Buffer Size */ 186 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 187 /* memtest works on */ 188 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 189 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 190 0x01F00000) /* 31MB */ 191 192 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 193 /* address */ 194 195 /* 196 * AM3517 has 12 GP timers, they can be driven by the system clock 197 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 198 * This rate is divided by a local divisor. 199 */ 200 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 201 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 202 203 /*----------------------------------------------------------------------- 204 * Physical Memory Map 205 */ 206 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 207 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 208 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 209 210 /*----------------------------------------------------------------------- 211 * FLASH and environment organization 212 */ 213 214 /* **** PISMO SUPPORT *** */ 215 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 216 /* on one chip */ 217 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 218 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 219 220 #define CONFIG_SYS_FLASH_BASE NAND_BASE 221 222 /* Monitor at start of flash */ 223 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 224 225 #define CONFIG_NAND_OMAP_GPMC 226 #define CONFIG_ENV_IS_IN_NAND 1 227 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 228 229 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 230 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 231 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 232 233 /*----------------------------------------------------------------------- 234 * CFI FLASH driver setup 235 */ 236 /* timeout values are in ticks */ 237 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 238 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 239 240 /* Flash banks JFFS2 should use */ 241 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 242 CONFIG_SYS_MAX_NAND_DEVICE) 243 #define CONFIG_SYS_JFFS2_MEM_NAND 244 /* use flash_info[2] */ 245 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 246 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 247 248 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 249 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 250 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 251 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 252 CONFIG_SYS_INIT_RAM_SIZE - \ 253 GENERATED_GBL_DATA_SIZE) 254 255 /* Defines for SPL */ 256 #define CONFIG_SPL_FRAMEWORK 257 #define CONFIG_SPL_BOARD_INIT 258 #define CONFIG_SPL_NAND_SIMPLE 259 #define CONFIG_SPL_TEXT_BASE 0x40200800 260 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 261 CONFIG_SPL_TEXT_BASE) 262 263 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 264 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 265 266 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 267 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 268 269 #define CONFIG_SPL_NAND_BASE 270 #define CONFIG_SPL_NAND_DRIVERS 271 #define CONFIG_SPL_NAND_ECC 272 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 273 274 /* NAND boot config */ 275 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 276 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 277 #define CONFIG_SYS_NAND_PAGE_COUNT 64 278 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 279 #define CONFIG_SYS_NAND_OOBSIZE 64 280 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 281 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 282 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 283 10, 11, 12, 13} 284 #define CONFIG_SYS_NAND_ECCSIZE 512 285 #define CONFIG_SYS_NAND_ECCBYTES 3 286 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 287 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 288 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 289 290 /* 291 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 292 * 64 bytes before this address should be set aside for u-boot.img's 293 * header. That is 0x800FFFC0--0x80100000 should not be used for any 294 * other needs. 295 */ 296 #define CONFIG_SYS_TEXT_BASE 0x80100000 297 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 298 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 299 300 #endif /* __CONFIG_H */ 301