1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 20 #include <asm/arch/cpu.h> /* get chip and board defs */ 21 #include <asm/arch/omap.h> 22 23 /* Clock Defines */ 24 #define V_OSCK 26000000 /* Clock output from T2 */ 25 #define V_SCLK (V_OSCK >> 1) 26 27 #define CONFIG_MISC_INIT_R 28 29 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 30 #define CONFIG_SETUP_MEMORY_TAGS 1 31 #define CONFIG_INITRD_TAG 1 32 #define CONFIG_REVISION_TAG 1 33 34 /* 35 * Size of malloc() pool 36 */ 37 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 38 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 39 /* initial data */ 40 /* 41 * DDR related 42 */ 43 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 44 45 /* 46 * Hardware drivers 47 */ 48 49 /* 50 * NS16550 Configuration 51 */ 52 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 53 54 #define CONFIG_SYS_NS16550_SERIAL 55 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 56 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 57 58 /* 59 * select serial console configuration 60 */ 61 #define CONFIG_CONS_INDEX 3 62 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 63 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 64 65 /* allow to overwrite serial and ethaddr */ 66 #define CONFIG_ENV_OVERWRITE 67 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 68 115200} 69 70 /* 71 * USB configuration 72 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 73 * Enable CONFIG_USB_MUSB_UDC for Device functionalities. 74 */ 75 76 #ifdef CONFIG_USB_AM35X 77 78 #ifdef CONFIG_USB_MUSB_HCD 79 80 #ifdef CONFIG_USB_KEYBOARD 81 #define CONFIG_PREBOOT "usb start" 82 #endif /* CONFIG_USB_KEYBOARD */ 83 84 #endif /* CONFIG_USB_MUSB_HCD */ 85 86 #ifdef CONFIG_USB_MUSB_UDC 87 /* USB device configuration */ 88 #define CONFIG_USB_DEVICE 1 89 #define CONFIG_USB_TTY 1 90 /* Change these to suit your needs */ 91 #define CONFIG_USBD_VENDORID 0x0451 92 #define CONFIG_USBD_PRODUCTID 0x5678 93 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 94 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 95 #endif /* CONFIG_USB_MUSB_UDC */ 96 97 #endif /* CONFIG_USB_AM35X */ 98 99 #define CONFIG_SYS_I2C 100 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 101 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 102 103 /* 104 * Board NAND Info. 105 */ 106 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 107 /* to access nand */ 108 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 109 /* to access */ 110 /* nand at CS0 */ 111 112 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 113 /* NAND devices */ 114 115 #define CONFIG_JFFS2_NAND 116 /* nand device jffs2 lives on */ 117 #define CONFIG_JFFS2_DEV "nand0" 118 /* start of jffs2 partition */ 119 #define CONFIG_JFFS2_PART_OFFSET 0x680000 120 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 121 122 /* Environment information */ 123 124 #define CONFIG_BOOTFILE "uImage" 125 126 #define CONFIG_EXTRA_ENV_SETTINGS \ 127 "loadaddr=0x82000000\0" \ 128 "console=ttyS2,115200n8\0" \ 129 "mmcdev=0\0" \ 130 "mmcargs=setenv bootargs console=${console} " \ 131 "root=/dev/mmcblk0p2 rw " \ 132 "rootfstype=ext3 rootwait\0" \ 133 "nandargs=setenv bootargs console=${console} " \ 134 "root=/dev/mtdblock4 rw " \ 135 "rootfstype=jffs2\0" \ 136 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 137 "bootscript=echo Running bootscript from mmc ...; " \ 138 "source ${loadaddr}\0" \ 139 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 140 "mmcboot=echo Booting from mmc ...; " \ 141 "run mmcargs; " \ 142 "bootm ${loadaddr}\0" \ 143 "nandboot=echo Booting from nand ...; " \ 144 "run nandargs; " \ 145 "nand read ${loadaddr} 280000 400000; " \ 146 "bootm ${loadaddr}\0" \ 147 148 #define CONFIG_BOOTCOMMAND \ 149 "mmc dev ${mmcdev}; if mmc rescan; then " \ 150 "if run loadbootscript; then " \ 151 "run bootscript; " \ 152 "else " \ 153 "if run loaduimage; then " \ 154 "run mmcboot; " \ 155 "else run nandboot; " \ 156 "fi; " \ 157 "fi; " \ 158 "else run nandboot; fi" 159 160 #define CONFIG_AUTO_COMPLETE 1 161 /* 162 * Miscellaneous configurable options 163 */ 164 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 165 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 166 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 167 /* args */ 168 /* memtest works on */ 169 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 170 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 171 0x01F00000) /* 31MB */ 172 173 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 174 /* address */ 175 176 /* 177 * AM3517 has 12 GP timers, they can be driven by the system clock 178 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 179 * This rate is divided by a local divisor. 180 */ 181 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 182 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 183 184 /*----------------------------------------------------------------------- 185 * Physical Memory Map 186 */ 187 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 188 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 189 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 190 191 /*----------------------------------------------------------------------- 192 * FLASH and environment organization 193 */ 194 195 /* **** PISMO SUPPORT *** */ 196 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 197 /* on one chip */ 198 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 199 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 200 201 #define CONFIG_SYS_FLASH_BASE NAND_BASE 202 203 /* Monitor at start of flash */ 204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 205 206 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 207 #define CONFIG_ENV_OFFSET 0x260000 208 #define CONFIG_ENV_ADDR 0x260000 209 210 /*----------------------------------------------------------------------- 211 * CFI FLASH driver setup 212 */ 213 /* timeout values are in ticks */ 214 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 215 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 216 217 /* Flash banks JFFS2 should use */ 218 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 219 CONFIG_SYS_MAX_NAND_DEVICE) 220 #define CONFIG_SYS_JFFS2_MEM_NAND 221 /* use flash_info[2] */ 222 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 223 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 224 225 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 226 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 227 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 228 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 229 CONFIG_SYS_INIT_RAM_SIZE - \ 230 GENERATED_GBL_DATA_SIZE) 231 232 /* Defines for SPL */ 233 #define CONFIG_SPL_FRAMEWORK 234 #define CONFIG_SPL_TEXT_BASE 0x40200800 235 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 236 CONFIG_SPL_TEXT_BASE) 237 238 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 239 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 240 241 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 242 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 243 244 #define CONFIG_SPL_NAND_BASE 245 #define CONFIG_SPL_NAND_DRIVERS 246 #define CONFIG_SPL_NAND_ECC 247 248 /* NAND boot config */ 249 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 250 #define CONFIG_SYS_NAND_PAGE_COUNT 64 251 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 252 #define CONFIG_SYS_NAND_OOBSIZE 64 253 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 254 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 255 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 256 10, 11, 12, 13} 257 #define CONFIG_SYS_NAND_ECCSIZE 512 258 #define CONFIG_SYS_NAND_ECCBYTES 3 259 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 260 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 261 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 262 263 /* 264 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 265 * 64 bytes before this address should be set aside for u-boot.img's 266 * header. That is 0x800FFFC0--0x80100000 should not be used for any 267 * other needs. 268 */ 269 #define CONFIG_SYS_TEXT_BASE 0x80100000 270 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 271 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 272 273 #endif /* __CONFIG_H */ 274