1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ 21 /* Common ARM Erratas */ 22 #define CONFIG_ARM_ERRATA_454179 23 #define CONFIG_ARM_ERRATA_430973 24 #define CONFIG_ARM_ERRATA_621766 25 26 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 27 28 #include <asm/arch/cpu.h> /* get chip and board defs */ 29 #include <asm/arch/omap.h> 30 31 /* Clock Defines */ 32 #define V_OSCK 26000000 /* Clock output from T2 */ 33 #define V_SCLK (V_OSCK >> 1) 34 35 #define CONFIG_MISC_INIT_R 36 37 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 38 #define CONFIG_SETUP_MEMORY_TAGS 1 39 #define CONFIG_INITRD_TAG 1 40 #define CONFIG_REVISION_TAG 1 41 42 /* 43 * Size of malloc() pool 44 */ 45 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 46 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 47 /* initial data */ 48 /* 49 * DDR related 50 */ 51 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 52 53 /* 54 * Hardware drivers 55 */ 56 57 /* 58 * NS16550 Configuration 59 */ 60 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 61 62 #define CONFIG_SYS_NS16550_SERIAL 63 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 64 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 65 66 /* 67 * select serial console configuration 68 */ 69 #define CONFIG_CONS_INDEX 3 70 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 71 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 72 73 /* allow to overwrite serial and ethaddr */ 74 #define CONFIG_ENV_OVERWRITE 75 #define CONFIG_BAUDRATE 115200 76 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 77 115200} 78 79 /* 80 * USB configuration 81 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 82 * Enable CONFIG_USB_MUSB_UDC for Device functionalities. 83 */ 84 #define CONFIG_USB_AM35X 1 85 #define CONFIG_USB_MUSB_HCD 1 86 87 #ifdef CONFIG_USB_AM35X 88 89 #ifdef CONFIG_USB_MUSB_HCD 90 91 #ifdef CONFIG_USB_KEYBOARD 92 #define CONFIG_SYS_USB_EVENT_POLL 93 #define CONFIG_PREBOOT "usb start" 94 #endif /* CONFIG_USB_KEYBOARD */ 95 96 #endif /* CONFIG_USB_MUSB_HCD */ 97 98 #ifdef CONFIG_USB_MUSB_UDC 99 /* USB device configuration */ 100 #define CONFIG_USB_DEVICE 1 101 #define CONFIG_USB_TTY 1 102 /* Change these to suit your needs */ 103 #define CONFIG_USBD_VENDORID 0x0451 104 #define CONFIG_USBD_PRODUCTID 0x5678 105 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 106 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 107 #endif /* CONFIG_USB_MUSB_UDC */ 108 109 #endif /* CONFIG_USB_AM35X */ 110 111 /* commands to include */ 112 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 113 114 #define CONFIG_CMD_NAND /* NAND support */ 115 116 #define CONFIG_SYS_I2C 117 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 118 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 119 #define CONFIG_SYS_I2C_OMAP34XX 120 121 /* 122 * Board NAND Info. 123 */ 124 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 125 /* to access nand */ 126 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 127 /* to access */ 128 /* nand at CS0 */ 129 130 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 131 /* NAND devices */ 132 133 #define CONFIG_JFFS2_NAND 134 /* nand device jffs2 lives on */ 135 #define CONFIG_JFFS2_DEV "nand0" 136 /* start of jffs2 partition */ 137 #define CONFIG_JFFS2_PART_OFFSET 0x680000 138 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 139 140 /* Environment information */ 141 142 #define CONFIG_BOOTFILE "uImage" 143 144 #define CONFIG_EXTRA_ENV_SETTINGS \ 145 "loadaddr=0x82000000\0" \ 146 "console=ttyS2,115200n8\0" \ 147 "mmcdev=0\0" \ 148 "mmcargs=setenv bootargs console=${console} " \ 149 "root=/dev/mmcblk0p2 rw " \ 150 "rootfstype=ext3 rootwait\0" \ 151 "nandargs=setenv bootargs console=${console} " \ 152 "root=/dev/mtdblock4 rw " \ 153 "rootfstype=jffs2\0" \ 154 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 155 "bootscript=echo Running bootscript from mmc ...; " \ 156 "source ${loadaddr}\0" \ 157 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 158 "mmcboot=echo Booting from mmc ...; " \ 159 "run mmcargs; " \ 160 "bootm ${loadaddr}\0" \ 161 "nandboot=echo Booting from nand ...; " \ 162 "run nandargs; " \ 163 "nand read ${loadaddr} 280000 400000; " \ 164 "bootm ${loadaddr}\0" \ 165 166 #define CONFIG_BOOTCOMMAND \ 167 "mmc dev ${mmcdev}; if mmc rescan; then " \ 168 "if run loadbootscript; then " \ 169 "run bootscript; " \ 170 "else " \ 171 "if run loaduimage; then " \ 172 "run mmcboot; " \ 173 "else run nandboot; " \ 174 "fi; " \ 175 "fi; " \ 176 "else run nandboot; fi" 177 178 #define CONFIG_AUTO_COMPLETE 1 179 /* 180 * Miscellaneous configurable options 181 */ 182 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 183 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 184 /* Print Buffer Size */ 185 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 186 sizeof(CONFIG_SYS_PROMPT) + 16) 187 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 188 /* args */ 189 /* Boot Argument Buffer Size */ 190 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 191 /* memtest works on */ 192 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 193 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 194 0x01F00000) /* 31MB */ 195 196 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 197 /* address */ 198 199 /* 200 * AM3517 has 12 GP timers, they can be driven by the system clock 201 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 202 * This rate is divided by a local divisor. 203 */ 204 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 205 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 206 207 /*----------------------------------------------------------------------- 208 * Physical Memory Map 209 */ 210 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 211 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 212 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 213 214 /*----------------------------------------------------------------------- 215 * FLASH and environment organization 216 */ 217 218 /* **** PISMO SUPPORT *** */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 220 /* on one chip */ 221 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 222 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 223 224 #define CONFIG_SYS_FLASH_BASE NAND_BASE 225 226 /* Monitor at start of flash */ 227 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 228 229 #define CONFIG_NAND_OMAP_GPMC 230 #define CONFIG_ENV_IS_IN_NAND 1 231 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 232 233 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 234 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 235 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 236 237 /*----------------------------------------------------------------------- 238 * CFI FLASH driver setup 239 */ 240 /* timeout values are in ticks */ 241 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 242 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 243 244 /* Flash banks JFFS2 should use */ 245 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 246 CONFIG_SYS_MAX_NAND_DEVICE) 247 #define CONFIG_SYS_JFFS2_MEM_NAND 248 /* use flash_info[2] */ 249 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 250 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 251 252 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 253 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 254 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 255 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 256 CONFIG_SYS_INIT_RAM_SIZE - \ 257 GENERATED_GBL_DATA_SIZE) 258 259 /* Defines for SPL */ 260 #define CONFIG_SPL_FRAMEWORK 261 #define CONFIG_SPL_BOARD_INIT 262 #define CONFIG_SPL_NAND_SIMPLE 263 #define CONFIG_SPL_TEXT_BASE 0x40200800 264 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 265 CONFIG_SPL_TEXT_BASE) 266 267 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 268 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 269 270 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 271 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 272 273 #define CONFIG_SPL_NAND_BASE 274 #define CONFIG_SPL_NAND_DRIVERS 275 #define CONFIG_SPL_NAND_ECC 276 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 277 278 /* NAND boot config */ 279 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 280 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 281 #define CONFIG_SYS_NAND_PAGE_COUNT 64 282 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 283 #define CONFIG_SYS_NAND_OOBSIZE 64 284 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 285 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 286 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 287 10, 11, 12, 13} 288 #define CONFIG_SYS_NAND_ECCSIZE 512 289 #define CONFIG_SYS_NAND_ECCBYTES 3 290 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 291 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 292 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 293 294 /* 295 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 296 * 64 bytes before this address should be set aside for u-boot.img's 297 * header. That is 0x800FFFC0--0x80100000 should not be used for any 298 * other needs. 299 */ 300 #define CONFIG_SYS_TEXT_BASE 0x80100000 301 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 302 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 303 304 #endif /* __CONFIG_H */ 305