1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ 21 #define CONFIG_OMAP_COMMON 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 28 29 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/omap.h> 31 32 /* 33 * Display CPU and Board information 34 */ 35 #define CONFIG_DISPLAY_CPUINFO 1 36 #define CONFIG_DISPLAY_BOARDINFO 1 37 38 /* Clock Defines */ 39 #define V_OSCK 26000000 /* Clock output from T2 */ 40 #define V_SCLK (V_OSCK >> 1) 41 42 #define CONFIG_MISC_INIT_R 43 44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 45 #define CONFIG_SETUP_MEMORY_TAGS 1 46 #define CONFIG_INITRD_TAG 1 47 #define CONFIG_REVISION_TAG 1 48 49 /* 50 * Size of malloc() pool 51 */ 52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 53 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 54 /* initial data */ 55 /* 56 * DDR related 57 */ 58 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 59 60 /* 61 * Hardware drivers 62 */ 63 64 /* 65 * NS16550 Configuration 66 */ 67 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 68 69 #define CONFIG_SYS_NS16550_SERIAL 70 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 71 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 72 73 /* 74 * select serial console configuration 75 */ 76 #define CONFIG_CONS_INDEX 3 77 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 78 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 79 80 /* allow to overwrite serial and ethaddr */ 81 #define CONFIG_ENV_OVERWRITE 82 #define CONFIG_BAUDRATE 115200 83 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 84 115200} 85 #define CONFIG_GENERIC_MMC 1 86 #define CONFIG_MMC 1 87 #define CONFIG_OMAP_HSMMC 1 88 #define CONFIG_DOS_PARTITION 1 89 90 /* 91 * USB configuration 92 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 93 * Enable CONFIG_USB_MUSB_UDC for Device functionalities. 94 */ 95 #define CONFIG_USB_AM35X 1 96 #define CONFIG_USB_MUSB_HCD 1 97 98 #ifdef CONFIG_USB_AM35X 99 100 #ifdef CONFIG_USB_MUSB_HCD 101 102 #define CONFIG_USB_STORAGE 103 #define CONGIG_CMD_STORAGE 104 105 #ifdef CONFIG_USB_KEYBOARD 106 #define CONFIG_SYS_USB_EVENT_POLL 107 #define CONFIG_PREBOOT "usb start" 108 #endif /* CONFIG_USB_KEYBOARD */ 109 110 #endif /* CONFIG_USB_MUSB_HCD */ 111 112 #ifdef CONFIG_USB_MUSB_UDC 113 /* USB device configuration */ 114 #define CONFIG_USB_DEVICE 1 115 #define CONFIG_USB_TTY 1 116 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 117 /* Change these to suit your needs */ 118 #define CONFIG_USBD_VENDORID 0x0451 119 #define CONFIG_USBD_PRODUCTID 0x5678 120 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 121 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 122 #endif /* CONFIG_USB_MUSB_UDC */ 123 124 #endif /* CONFIG_USB_AM35X */ 125 126 /* commands to include */ 127 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 128 129 #define CONFIG_CMD_NAND /* NAND support */ 130 131 #define CONFIG_SYS_NO_FLASH 132 #define CONFIG_SYS_I2C 133 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 134 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 135 #define CONFIG_SYS_I2C_OMAP34XX 136 137 /* 138 * Board NAND Info. 139 */ 140 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 141 /* to access nand */ 142 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 143 /* to access */ 144 /* nand at CS0 */ 145 146 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 147 /* NAND devices */ 148 149 #define CONFIG_JFFS2_NAND 150 /* nand device jffs2 lives on */ 151 #define CONFIG_JFFS2_DEV "nand0" 152 /* start of jffs2 partition */ 153 #define CONFIG_JFFS2_PART_OFFSET 0x680000 154 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 155 156 /* Environment information */ 157 158 #define CONFIG_BOOTFILE "uImage" 159 160 #define CONFIG_EXTRA_ENV_SETTINGS \ 161 "loadaddr=0x82000000\0" \ 162 "console=ttyS2,115200n8\0" \ 163 "mmcdev=0\0" \ 164 "mmcargs=setenv bootargs console=${console} " \ 165 "root=/dev/mmcblk0p2 rw " \ 166 "rootfstype=ext3 rootwait\0" \ 167 "nandargs=setenv bootargs console=${console} " \ 168 "root=/dev/mtdblock4 rw " \ 169 "rootfstype=jffs2\0" \ 170 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 171 "bootscript=echo Running bootscript from mmc ...; " \ 172 "source ${loadaddr}\0" \ 173 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 174 "mmcboot=echo Booting from mmc ...; " \ 175 "run mmcargs; " \ 176 "bootm ${loadaddr}\0" \ 177 "nandboot=echo Booting from nand ...; " \ 178 "run nandargs; " \ 179 "nand read ${loadaddr} 280000 400000; " \ 180 "bootm ${loadaddr}\0" \ 181 182 #define CONFIG_BOOTCOMMAND \ 183 "mmc dev ${mmcdev}; if mmc rescan; then " \ 184 "if run loadbootscript; then " \ 185 "run bootscript; " \ 186 "else " \ 187 "if run loaduimage; then " \ 188 "run mmcboot; " \ 189 "else run nandboot; " \ 190 "fi; " \ 191 "fi; " \ 192 "else run nandboot; fi" 193 194 #define CONFIG_AUTO_COMPLETE 1 195 /* 196 * Miscellaneous configurable options 197 */ 198 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 199 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 200 /* Print Buffer Size */ 201 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 202 sizeof(CONFIG_SYS_PROMPT) + 16) 203 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 204 /* args */ 205 /* Boot Argument Buffer Size */ 206 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 207 /* memtest works on */ 208 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 209 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 210 0x01F00000) /* 31MB */ 211 212 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 213 /* address */ 214 215 /* 216 * AM3517 has 12 GP timers, they can be driven by the system clock 217 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 218 * This rate is divided by a local divisor. 219 */ 220 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 221 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 222 223 /*----------------------------------------------------------------------- 224 * Physical Memory Map 225 */ 226 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 227 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 228 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 229 230 /*----------------------------------------------------------------------- 231 * FLASH and environment organization 232 */ 233 234 /* **** PISMO SUPPORT *** */ 235 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 236 /* on one chip */ 237 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 238 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 239 240 #define CONFIG_SYS_FLASH_BASE NAND_BASE 241 242 /* Monitor at start of flash */ 243 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 244 245 #define CONFIG_NAND_OMAP_GPMC 246 #define CONFIG_ENV_IS_IN_NAND 1 247 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 248 249 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 250 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 251 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 252 253 /*----------------------------------------------------------------------- 254 * CFI FLASH driver setup 255 */ 256 /* timeout values are in ticks */ 257 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 258 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 259 260 /* Flash banks JFFS2 should use */ 261 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 262 CONFIG_SYS_MAX_NAND_DEVICE) 263 #define CONFIG_SYS_JFFS2_MEM_NAND 264 /* use flash_info[2] */ 265 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 266 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 267 268 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 269 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 270 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 271 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 272 CONFIG_SYS_INIT_RAM_SIZE - \ 273 GENERATED_GBL_DATA_SIZE) 274 275 /* Defines for SPL */ 276 #define CONFIG_SPL_FRAMEWORK 277 #define CONFIG_SPL_BOARD_INIT 278 #define CONFIG_SPL_NAND_SIMPLE 279 #define CONFIG_SPL_TEXT_BASE 0x40200800 280 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 281 282 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 283 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 284 285 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 286 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 287 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 288 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 289 290 #define CONFIG_SPL_LIBCOMMON_SUPPORT 291 #define CONFIG_SPL_LIBDISK_SUPPORT 292 #define CONFIG_SPL_I2C_SUPPORT 293 #define CONFIG_SPL_LIBGENERIC_SUPPORT 294 #define CONFIG_SPL_MMC_SUPPORT 295 #define CONFIG_SPL_FAT_SUPPORT 296 #define CONFIG_SPL_SERIAL_SUPPORT 297 #define CONFIG_SPL_NAND_SUPPORT 298 #define CONFIG_SPL_NAND_BASE 299 #define CONFIG_SPL_NAND_DRIVERS 300 #define CONFIG_SPL_NAND_ECC 301 #define CONFIG_SPL_POWER_SUPPORT 302 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 303 304 /* NAND boot config */ 305 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 306 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 307 #define CONFIG_SYS_NAND_PAGE_COUNT 64 308 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 309 #define CONFIG_SYS_NAND_OOBSIZE 64 310 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 311 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 312 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 313 10, 11, 12, 13} 314 #define CONFIG_SYS_NAND_ECCSIZE 512 315 #define CONFIG_SYS_NAND_ECCBYTES 3 316 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 317 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 318 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 319 320 /* 321 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 322 * 64 bytes before this address should be set aside for u-boot.img's 323 * header. That is 0x800FFFC0--0x80100000 should not be used for any 324 * other needs. 325 */ 326 #define CONFIG_SYS_TEXT_BASE 0x80100000 327 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 328 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 329 330 #endif /* __CONFIG_H */ 331