1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 32 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 33 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ 34 35 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 36 37 #include <asm/arch/cpu.h> /* get chip and board defs */ 38 #include <asm/arch/omap3.h> 39 40 /* 41 * Display CPU and Board information 42 */ 43 #define CONFIG_DISPLAY_CPUINFO 1 44 #define CONFIG_DISPLAY_BOARDINFO 1 45 46 /* Clock Defines */ 47 #define V_OSCK 26000000 /* Clock output from T2 */ 48 #define V_SCLK (V_OSCK >> 1) 49 50 #undef CONFIG_USE_IRQ /* no support for IRQs */ 51 #define CONFIG_MISC_INIT_R 52 53 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 54 #define CONFIG_SETUP_MEMORY_TAGS 1 55 #define CONFIG_INITRD_TAG 1 56 #define CONFIG_REVISION_TAG 1 57 58 /* 59 * Size of malloc() pool 60 */ 61 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 63 /* initial data */ 64 /* 65 * DDR related 66 */ 67 #define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */ 68 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 69 70 /* 71 * Hardware drivers 72 */ 73 74 /* 75 * NS16550 Configuration 76 */ 77 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 78 79 #define CONFIG_SYS_NS16550 80 #define CONFIG_SYS_NS16550_SERIAL 81 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 82 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 83 84 /* 85 * select serial console configuration 86 */ 87 #define CONFIG_CONS_INDEX 3 88 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 89 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 90 91 /* allow to overwrite serial and ethaddr */ 92 #define CONFIG_ENV_OVERWRITE 93 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 95 115200} 96 #define CONFIG_GENERIC_MMC 1 97 #define CONFIG_MMC 1 98 #define CONFIG_OMAP_HSMMC 1 99 #define CONFIG_DOS_PARTITION 1 100 101 /* 102 * USB configuration 103 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 104 * Enable CONFIG_MUSB_UDC for Device functionalities. 105 */ 106 #define CONFIG_USB_AM35X 1 107 #define CONFIG_MUSB_HCD 1 108 109 #ifdef CONFIG_USB_AM35X 110 111 #ifdef CONFIG_MUSB_HCD 112 #define CONFIG_CMD_USB 113 114 #define CONFIG_USB_STORAGE 115 #define CONGIG_CMD_STORAGE 116 #define CONFIG_CMD_FAT 117 118 #ifdef CONFIG_USB_KEYBOARD 119 #define CONFIG_SYS_USB_EVENT_POLL 120 #define CONFIG_PREBOOT "usb start" 121 #endif /* CONFIG_USB_KEYBOARD */ 122 123 #endif /* CONFIG_MUSB_HCD */ 124 125 #ifdef CONFIG_MUSB_UDC 126 /* USB device configuration */ 127 #define CONFIG_USB_DEVICE 1 128 #define CONFIG_USB_TTY 1 129 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 130 /* Change these to suit your needs */ 131 #define CONFIG_USBD_VENDORID 0x0451 132 #define CONFIG_USBD_PRODUCTID 0x5678 133 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 134 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 135 #endif /* CONFIG_MUSB_UDC */ 136 137 #endif /* CONFIG_USB_AM35X */ 138 139 /* commands to include */ 140 #include <config_cmd_default.h> 141 142 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 143 #define CONFIG_CMD_FAT /* FAT support */ 144 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 145 146 #define CONFIG_CMD_I2C /* I2C serial bus support */ 147 #define CONFIG_CMD_MMC /* MMC support */ 148 #define CONFIG_CMD_NAND /* NAND support */ 149 #define CONFIG_CMD_DHCP 150 #define CONFIG_CMD_PING 151 152 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 153 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 154 #undef CONFIG_CMD_IMI /* iminfo */ 155 #undef CONFIG_CMD_IMLS /* List all found images */ 156 157 #define CONFIG_SYS_NO_FLASH 158 #define CONFIG_HARD_I2C 1 159 #define CONFIG_SYS_I2C_SPEED 100000 160 #define CONFIG_SYS_I2C_SLAVE 1 161 #define CONFIG_SYS_I2C_BUS 0 162 #define CONFIG_SYS_I2C_BUS_SELECT 1 163 #define CONFIG_DRIVER_OMAP34XX_I2C 1 164 165 #undef CONFIG_CMD_NET 166 #undef CONFIG_CMD_NFS 167 /* 168 * Board NAND Info. 169 */ 170 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 171 /* to access nand */ 172 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 173 /* to access */ 174 /* nand at CS0 */ 175 176 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 177 /* NAND devices */ 178 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 179 180 #define CONFIG_JFFS2_NAND 181 /* nand device jffs2 lives on */ 182 #define CONFIG_JFFS2_DEV "nand0" 183 /* start of jffs2 partition */ 184 #define CONFIG_JFFS2_PART_OFFSET 0x680000 185 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 186 187 /* Environment information */ 188 #define CONFIG_BOOTDELAY 10 189 190 #define CONFIG_BOOTFILE "uImage" 191 192 #define CONFIG_EXTRA_ENV_SETTINGS \ 193 "loadaddr=0x82000000\0" \ 194 "console=ttyS2,115200n8\0" \ 195 "mmcdev=0\0" \ 196 "mmcargs=setenv bootargs console=${console} " \ 197 "root=/dev/mmcblk0p2 rw " \ 198 "rootfstype=ext3 rootwait\0" \ 199 "nandargs=setenv bootargs console=${console} " \ 200 "root=/dev/mtdblock4 rw " \ 201 "rootfstype=jffs2\0" \ 202 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 203 "bootscript=echo Running bootscript from mmc ...; " \ 204 "source ${loadaddr}\0" \ 205 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 206 "mmcboot=echo Booting from mmc ...; " \ 207 "run mmcargs; " \ 208 "bootm ${loadaddr}\0" \ 209 "nandboot=echo Booting from nand ...; " \ 210 "run nandargs; " \ 211 "nand read ${loadaddr} 280000 400000; " \ 212 "bootm ${loadaddr}\0" \ 213 214 #define CONFIG_BOOTCOMMAND \ 215 "if mmc rescan ${mmcdev}; then " \ 216 "if run loadbootscript; then " \ 217 "run bootscript; " \ 218 "else " \ 219 "if run loaduimage; then " \ 220 "run mmcboot; " \ 221 "else run nandboot; " \ 222 "fi; " \ 223 "fi; " \ 224 "else run nandboot; fi" 225 226 #define CONFIG_AUTO_COMPLETE 1 227 /* 228 * Miscellaneous configurable options 229 */ 230 #define V_PROMPT "AM3517_CRANE # " 231 232 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 233 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 234 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 235 #define CONFIG_SYS_PROMPT V_PROMPT 236 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 237 /* Print Buffer Size */ 238 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 239 sizeof(CONFIG_SYS_PROMPT) + 16) 240 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 241 /* args */ 242 /* Boot Argument Buffer Size */ 243 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 244 /* memtest works on */ 245 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 246 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 247 0x01F00000) /* 31MB */ 248 249 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 250 /* address */ 251 252 /* 253 * AM3517 has 12 GP timers, they can be driven by the system clock 254 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 255 * This rate is divided by a local divisor. 256 */ 257 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 258 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 259 #define CONFIG_SYS_HZ 1000 260 261 /*----------------------------------------------------------------------- 262 * Stack sizes 263 * 264 * The stack sizes are set up in start.S using the settings below 265 */ 266 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 267 #ifdef CONFIG_USE_IRQ 268 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 269 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 270 #endif 271 272 /*----------------------------------------------------------------------- 273 * Physical Memory Map 274 */ 275 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 276 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 277 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 278 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 279 280 /* SDRAM Bank Allocation method */ 281 #define SDRC_R_B_C 1 282 283 /*----------------------------------------------------------------------- 284 * FLASH and environment organization 285 */ 286 287 /* **** PISMO SUPPORT *** */ 288 289 /* Configure the PISMO */ 290 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 291 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 292 293 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 294 /* on one chip */ 295 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 296 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 297 298 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 299 300 /* Monitor at start of flash */ 301 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 302 303 #define CONFIG_NAND_OMAP_GPMC 304 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 305 #define CONFIG_ENV_IS_IN_NAND 1 306 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 307 308 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 309 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 310 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 311 312 /*----------------------------------------------------------------------- 313 * CFI FLASH driver setup 314 */ 315 /* timeout values are in ticks */ 316 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 317 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 318 319 /* Flash banks JFFS2 should use */ 320 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 321 CONFIG_SYS_MAX_NAND_DEVICE) 322 #define CONFIG_SYS_JFFS2_MEM_NAND 323 /* use flash_info[2] */ 324 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 325 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 326 327 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 328 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 329 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 330 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 331 CONFIG_SYS_INIT_RAM_SIZE - \ 332 GENERATED_GBL_DATA_SIZE) 333 #endif /* __CONFIG_H */ 334