1 /*
2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
3  *
4  * Author: Srinath.R <srinath@mistralsolutions.com>
5  *
6  * Based on include/configs/am3517evm.h
7  *
8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 /*
17  * High Level Configuration Options
18  */
19 #define CONFIG_OMAP		1	/* in a TI OMAP core */
20 #define CONFIG_OMAP3_AM3517CRANE	1	/* working with CRANEBOARD */
21 /* Common ARM Erratas */
22 #define CONFIG_ARM_ERRATA_454179
23 #define CONFIG_ARM_ERRATA_430973
24 #define CONFIG_ARM_ERRATA_621766
25 
26 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
27 
28 #include <asm/arch/cpu.h>		/* get chip and board defs */
29 #include <asm/arch/omap.h>
30 
31 /* Clock Defines */
32 #define V_OSCK			26000000	/* Clock output from T2 */
33 #define V_SCLK			(V_OSCK >> 1)
34 
35 #define CONFIG_MISC_INIT_R
36 
37 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
38 #define CONFIG_SETUP_MEMORY_TAGS	1
39 #define CONFIG_INITRD_TAG		1
40 #define CONFIG_REVISION_TAG		1
41 
42 /*
43  * Size of malloc() pool
44  */
45 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
46 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
47 						/* initial data */
48 /*
49  * DDR related
50  */
51 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
52 
53 /*
54  * Hardware drivers
55  */
56 
57 /*
58  * NS16550 Configuration
59  */
60 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
61 
62 #define CONFIG_SYS_NS16550_SERIAL
63 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
64 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
65 
66 /*
67  * select serial console configuration
68  */
69 #define CONFIG_CONS_INDEX		3
70 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
71 #define CONFIG_SERIAL3			3	/* UART3 on CRANEBOARD */
72 
73 /* allow to overwrite serial and ethaddr */
74 #define CONFIG_ENV_OVERWRITE
75 #define CONFIG_BAUDRATE			115200
76 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
77 					115200}
78 #define CONFIG_GENERIC_MMC		1
79 #define CONFIG_DOS_PARTITION		1
80 
81 /*
82  * USB configuration
83  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
84  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
85  */
86 #define CONFIG_USB_AM35X		1
87 #define CONFIG_USB_MUSB_HCD			1
88 
89 #ifdef CONFIG_USB_AM35X
90 
91 #ifdef CONFIG_USB_MUSB_HCD
92 
93 #define CONGIG_CMD_STORAGE
94 
95 #ifdef CONFIG_USB_KEYBOARD
96 #define CONFIG_SYS_USB_EVENT_POLL
97 #define CONFIG_PREBOOT "usb start"
98 #endif /* CONFIG_USB_KEYBOARD */
99 
100 #endif /* CONFIG_USB_MUSB_HCD */
101 
102 #ifdef CONFIG_USB_MUSB_UDC
103 /* USB device configuration */
104 #define CONFIG_USB_DEVICE		1
105 #define CONFIG_USB_TTY			1
106 /* Change these to suit your needs */
107 #define CONFIG_USBD_VENDORID		0x0451
108 #define CONFIG_USBD_PRODUCTID		0x5678
109 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
110 #define CONFIG_USBD_PRODUCT_NAME	"AM3517CRANE"
111 #endif /* CONFIG_USB_MUSB_UDC */
112 
113 #endif /* CONFIG_USB_AM35X */
114 
115 /* commands to include */
116 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
117 
118 #define CONFIG_CMD_NAND		/* NAND support			*/
119 
120 #define CONFIG_SYS_NO_FLASH
121 #define CONFIG_SYS_I2C
122 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
123 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
124 #define CONFIG_SYS_I2C_OMAP34XX
125 
126 /*
127  * Board NAND Info.
128  */
129 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
130 							/* to access nand */
131 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
132 							/* to access */
133 							/* nand at CS0 */
134 
135 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
136 							/* NAND devices */
137 
138 #define CONFIG_JFFS2_NAND
139 /* nand device jffs2 lives on */
140 #define CONFIG_JFFS2_DEV		"nand0"
141 /* start of jffs2 partition */
142 #define CONFIG_JFFS2_PART_OFFSET	0x680000
143 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
144 
145 /* Environment information */
146 
147 #define CONFIG_BOOTFILE		"uImage"
148 
149 #define CONFIG_EXTRA_ENV_SETTINGS \
150 	"loadaddr=0x82000000\0" \
151 	"console=ttyS2,115200n8\0" \
152 	"mmcdev=0\0" \
153 	"mmcargs=setenv bootargs console=${console} " \
154 		"root=/dev/mmcblk0p2 rw " \
155 		"rootfstype=ext3 rootwait\0" \
156 	"nandargs=setenv bootargs console=${console} " \
157 		"root=/dev/mtdblock4 rw " \
158 		"rootfstype=jffs2\0" \
159 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
160 	"bootscript=echo Running bootscript from mmc ...; " \
161 		"source ${loadaddr}\0" \
162 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
163 	"mmcboot=echo Booting from mmc ...; " \
164 		"run mmcargs; " \
165 		"bootm ${loadaddr}\0" \
166 	"nandboot=echo Booting from nand ...; " \
167 		"run nandargs; " \
168 		"nand read ${loadaddr} 280000 400000; " \
169 		"bootm ${loadaddr}\0" \
170 
171 #define CONFIG_BOOTCOMMAND \
172 	"mmc dev ${mmcdev}; if mmc rescan; then " \
173 		"if run loadbootscript; then " \
174 			"run bootscript; " \
175 		"else " \
176 			"if run loaduimage; then " \
177 				"run mmcboot; " \
178 			"else run nandboot; " \
179 			"fi; " \
180 		"fi; " \
181 	"else run nandboot; fi"
182 
183 #define CONFIG_AUTO_COMPLETE	1
184 /*
185  * Miscellaneous configurable options
186  */
187 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
188 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
189 /* Print Buffer Size */
190 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
191 					sizeof(CONFIG_SYS_PROMPT) + 16)
192 #define CONFIG_SYS_MAXARGS		32	/* max number of command */
193 						/* args */
194 /* Boot Argument Buffer Size */
195 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
196 /* memtest works on */
197 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
198 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
199 					0x01F00000) /* 31MB */
200 
201 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
202 								/* address */
203 
204 /*
205  * AM3517 has 12 GP timers, they can be driven by the system clock
206  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
207  * This rate is divided by a local divisor.
208  */
209 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
210 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
211 
212 /*-----------------------------------------------------------------------
213  * Physical Memory Map
214  */
215 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
216 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
217 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
218 
219 /*-----------------------------------------------------------------------
220  * FLASH and environment organization
221  */
222 
223 /* **** PISMO SUPPORT *** */
224 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
225 						/* on one chip */
226 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
227 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
228 
229 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
230 
231 /* Monitor at start of flash */
232 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
233 
234 #define CONFIG_NAND_OMAP_GPMC
235 #define CONFIG_ENV_IS_IN_NAND		1
236 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
237 
238 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB sector */
239 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
240 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
241 
242 /*-----------------------------------------------------------------------
243  * CFI FLASH driver setup
244  */
245 /* timeout values are in ticks */
246 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
247 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
248 
249 /* Flash banks JFFS2 should use */
250 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
251 					CONFIG_SYS_MAX_NAND_DEVICE)
252 #define CONFIG_SYS_JFFS2_MEM_NAND
253 /* use flash_info[2] */
254 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
255 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
256 
257 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
258 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
259 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
260 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
261 					 CONFIG_SYS_INIT_RAM_SIZE - \
262 					 GENERATED_GBL_DATA_SIZE)
263 
264 /* Defines for SPL */
265 #define CONFIG_SPL_FRAMEWORK
266 #define CONFIG_SPL_BOARD_INIT
267 #define CONFIG_SPL_NAND_SIMPLE
268 #define CONFIG_SPL_TEXT_BASE		0x40200800
269 #define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
270 					 CONFIG_SPL_TEXT_BASE)
271 
272 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
273 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
274 
275 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
276 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
277 
278 #define CONFIG_SPL_NAND_BASE
279 #define CONFIG_SPL_NAND_DRIVERS
280 #define CONFIG_SPL_NAND_ECC
281 #define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"
282 
283 /* NAND boot config */
284 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
285 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
286 #define CONFIG_SYS_NAND_PAGE_COUNT	64
287 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
288 #define CONFIG_SYS_NAND_OOBSIZE		64
289 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
290 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
291 #define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
292 						10, 11, 12, 13}
293 #define CONFIG_SYS_NAND_ECCSIZE		512
294 #define CONFIG_SYS_NAND_ECCBYTES	3
295 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
296 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
297 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
298 
299 /*
300  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
301  * 64 bytes before this address should be set aside for u-boot.img's
302  * header. That is 0x800FFFC0--0x80100000 should not be used for any
303  * other needs.
304  */
305 #define CONFIG_SYS_TEXT_BASE		0x80100000
306 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
307 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
308 
309 #endif /* __CONFIG_H */
310