1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
4  *
5  * Author: Srinath.R <srinath@mistralsolutions.com>
6  *
7  * Based on include/configs/am3517evm.h
8  *
9  * Copyright (C) 2011 Mistral Solutions pvt Ltd
10  */
11 
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14 
15 /*
16  * High Level Configuration Options
17  */
18 
19 #include <asm/arch/cpu.h>		/* get chip and board defs */
20 #include <asm/arch/omap.h>
21 
22 /* Clock Defines */
23 #define V_OSCK			26000000	/* Clock output from T2 */
24 #define V_SCLK			(V_OSCK >> 1)
25 
26 #define CONFIG_MISC_INIT_R
27 
28 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
29 #define CONFIG_SETUP_MEMORY_TAGS	1
30 #define CONFIG_INITRD_TAG		1
31 #define CONFIG_REVISION_TAG		1
32 
33 /*
34  * Size of malloc() pool
35  */
36 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
37 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
38 						/* initial data */
39 /*
40  * DDR related
41  */
42 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
43 
44 /*
45  * Hardware drivers
46  */
47 
48 /*
49  * NS16550 Configuration
50  */
51 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
52 
53 #define CONFIG_SYS_NS16550_SERIAL
54 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
55 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
56 
57 /*
58  * select serial console configuration
59  */
60 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
61 #define CONFIG_SERIAL3			3	/* UART3 on CRANEBOARD */
62 
63 /* allow to overwrite serial and ethaddr */
64 #define CONFIG_ENV_OVERWRITE
65 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
66 					115200}
67 
68 /*
69  * USB configuration
70  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
71  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
72  */
73 
74 #ifdef CONFIG_USB_AM35X
75 
76 #ifdef CONFIG_USB_MUSB_HCD
77 
78 #ifdef CONFIG_USB_KEYBOARD
79 #define CONFIG_PREBOOT "usb start"
80 #endif /* CONFIG_USB_KEYBOARD */
81 
82 #endif /* CONFIG_USB_MUSB_HCD */
83 
84 #ifdef CONFIG_USB_MUSB_UDC
85 /* USB device configuration */
86 #define CONFIG_USB_DEVICE		1
87 #define CONFIG_USB_TTY			1
88 /* Change these to suit your needs */
89 #define CONFIG_USBD_VENDORID		0x0451
90 #define CONFIG_USBD_PRODUCTID		0x5678
91 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
92 #define CONFIG_USBD_PRODUCT_NAME	"AM3517CRANE"
93 #endif /* CONFIG_USB_MUSB_UDC */
94 
95 #endif /* CONFIG_USB_AM35X */
96 
97 #define CONFIG_SYS_I2C
98 
99 /*
100  * Board NAND Info.
101  */
102 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
103 							/* to access */
104 							/* nand at CS0 */
105 
106 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
107 							/* NAND devices */
108 
109 #define CONFIG_JFFS2_NAND
110 /* nand device jffs2 lives on */
111 #define CONFIG_JFFS2_DEV		"nand0"
112 /* start of jffs2 partition */
113 #define CONFIG_JFFS2_PART_OFFSET	0x680000
114 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
115 
116 /* Environment information */
117 
118 #define CONFIG_BOOTFILE		"uImage"
119 
120 #define CONFIG_EXTRA_ENV_SETTINGS \
121 	"loadaddr=0x82000000\0" \
122 	"console=ttyS2,115200n8\0" \
123 	"mmcdev=0\0" \
124 	"mmcargs=setenv bootargs console=${console} " \
125 		"root=/dev/mmcblk0p2 rw " \
126 		"rootfstype=ext3 rootwait\0" \
127 	"nandargs=setenv bootargs console=${console} " \
128 		"root=/dev/mtdblock4 rw " \
129 		"rootfstype=jffs2\0" \
130 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
131 	"bootscript=echo Running bootscript from mmc ...; " \
132 		"source ${loadaddr}\0" \
133 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
134 	"mmcboot=echo Booting from mmc ...; " \
135 		"run mmcargs; " \
136 		"bootm ${loadaddr}\0" \
137 	"nandboot=echo Booting from nand ...; " \
138 		"run nandargs; " \
139 		"nand read ${loadaddr} 280000 400000; " \
140 		"bootm ${loadaddr}\0" \
141 
142 #define CONFIG_BOOTCOMMAND \
143 	"mmc dev ${mmcdev}; if mmc rescan; then " \
144 		"if run loadbootscript; then " \
145 			"run bootscript; " \
146 		"else " \
147 			"if run loaduimage; then " \
148 				"run mmcboot; " \
149 			"else run nandboot; " \
150 			"fi; " \
151 		"fi; " \
152 	"else run nandboot; fi"
153 
154 /*
155  * Miscellaneous configurable options
156  */
157 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
158 #define CONFIG_SYS_MAXARGS		32	/* max number of command */
159 						/* args */
160 /* memtest works on */
161 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
162 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
163 					0x01F00000) /* 31MB */
164 
165 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
166 								/* address */
167 
168 /*
169  * AM3517 has 12 GP timers, they can be driven by the system clock
170  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
171  * This rate is divided by a local divisor.
172  */
173 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
174 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
175 
176 /*-----------------------------------------------------------------------
177  * Physical Memory Map
178  */
179 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
180 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
181 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
182 
183 /*-----------------------------------------------------------------------
184  * FLASH and environment organization
185  */
186 
187 /* **** PISMO SUPPORT *** */
188 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
189 						/* on one chip */
190 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
191 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
192 
193 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
194 
195 /* Monitor at start of flash */
196 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
197 
198 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB sector */
199 #define CONFIG_ENV_OFFSET		0x260000
200 #define CONFIG_ENV_ADDR			0x260000
201 
202 /*-----------------------------------------------------------------------
203  * CFI FLASH driver setup
204  */
205 /* timeout values are in ticks */
206 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
207 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
208 
209 /* Flash banks JFFS2 should use */
210 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
211 					CONFIG_SYS_MAX_NAND_DEVICE)
212 #define CONFIG_SYS_JFFS2_MEM_NAND
213 /* use flash_info[2] */
214 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
215 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
216 
217 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
218 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
219 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
220 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
221 					 CONFIG_SYS_INIT_RAM_SIZE - \
222 					 GENERATED_GBL_DATA_SIZE)
223 
224 /* Defines for SPL */
225 #define CONFIG_SPL_TEXT_BASE		0x40200800
226 #define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
227 					 CONFIG_SPL_TEXT_BASE)
228 
229 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
230 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
231 
232 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
233 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
234 
235 #define CONFIG_SPL_NAND_BASE
236 #define CONFIG_SPL_NAND_DRIVERS
237 #define CONFIG_SPL_NAND_ECC
238 
239 /* NAND boot config */
240 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
241 #define CONFIG_SYS_NAND_PAGE_COUNT	64
242 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
243 #define CONFIG_SYS_NAND_OOBSIZE		64
244 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
245 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
246 #define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
247 						10, 11, 12, 13}
248 #define CONFIG_SYS_NAND_ECCSIZE		512
249 #define CONFIG_SYS_NAND_ECCBYTES	3
250 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
251 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
252 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
253 
254 /*
255  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
256  * 64 bytes before this address should be set aside for u-boot.img's
257  * header. That is 0x800FFFC0--0x80100000 should not be used for any
258  * other needs.
259  */
260 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
261 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
262 
263 #endif /* __CONFIG_H */
264