1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
29d1b2987SEnric Balletbò i Serra /*
39d1b2987SEnric Balletbò i Serra  * am335x_sl50.h
49d1b2987SEnric Balletbò i Serra  *
59d1b2987SEnric Balletbò i Serra  * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
69d1b2987SEnric Balletbò i Serra  */
79d1b2987SEnric Balletbò i Serra 
89d1b2987SEnric Balletbò i Serra #ifndef __CONFIG_AM335X_EVM_H
99d1b2987SEnric Balletbò i Serra #define __CONFIG_AM335X_EVM_H
109d1b2987SEnric Balletbò i Serra 
119d1b2987SEnric Balletbò i Serra #include <configs/ti_am335x_common.h>
129d1b2987SEnric Balletbò i Serra 
139d1b2987SEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD
149d1b2987SEnric Balletbò i Serra # define CONFIG_TIMESTAMP
159d1b2987SEnric Balletbò i Serra #endif
169d1b2987SEnric Balletbò i Serra 
179d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_BOOTM_LEN		(16 << 20)
189d1b2987SEnric Balletbò i Serra 
199d1b2987SEnric Balletbò i Serra /*#define CONFIG_MACH_TYPE		3589	 Until the next sync */
209d1b2987SEnric Balletbò i Serra 
219d1b2987SEnric Balletbò i Serra /* Clock Defines */
229d1b2987SEnric Balletbò i Serra #define V_OSCK				24000000  /* Clock output from T2 */
239d1b2987SEnric Balletbò i Serra #define V_SCLK				(V_OSCK)
249d1b2987SEnric Balletbò i Serra 
259d1b2987SEnric Balletbò i Serra /* Always 128 KiB env size */
269d1b2987SEnric Balletbò i Serra #define CONFIG_ENV_SIZE			(128 << 10)
279d1b2987SEnric Balletbò i Serra 
289d1b2987SEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD
299d1b2987SEnric Balletbò i Serra 
309d1b2987SEnric Balletbò i Serra #define MEM_LAYOUT_ENV_SETTINGS \
319d1b2987SEnric Balletbò i Serra 	"scriptaddr=0x80000000\0" \
329d1b2987SEnric Balletbò i Serra 	"pxefile_addr_r=0x80100000\0" \
339d1b2987SEnric Balletbò i Serra 	"kernel_addr_r=0x82000000\0" \
349d1b2987SEnric Balletbò i Serra 	"fdt_addr_r=0x88000000\0" \
359d1b2987SEnric Balletbò i Serra 	"ramdisk_addr_r=0x88080000\0" \
369d1b2987SEnric Balletbò i Serra 
379d1b2987SEnric Balletbò i Serra #define BOOT_TARGET_DEVICES(func) \
389d1b2987SEnric Balletbò i Serra 	func(MMC, mmc, 0) \
399d1b2987SEnric Balletbò i Serra 	func(MMC, mmc, 1)
409d1b2987SEnric Balletbò i Serra 
419d1b2987SEnric Balletbò i Serra #define AM335XX_BOARD_FDTFILE \
429d1b2987SEnric Balletbò i Serra 	"fdtfile=am335x-sl50.dtb\0" \
439d1b2987SEnric Balletbò i Serra 
449d1b2987SEnric Balletbò i Serra #include <config_distro_bootcmd.h>
459d1b2987SEnric Balletbò i Serra 
469d1b2987SEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \
479d1b2987SEnric Balletbò i Serra 	AM335XX_BOARD_FDTFILE \
489d1b2987SEnric Balletbò i Serra 	MEM_LAYOUT_ENV_SETTINGS \
499d1b2987SEnric Balletbò i Serra 	BOOTENV
509d1b2987SEnric Balletbò i Serra 
519d1b2987SEnric Balletbò i Serra #endif
529d1b2987SEnric Balletbò i Serra 
539d1b2987SEnric Balletbò i Serra /* NS16550 Configuration */
549d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
559d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
569d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
579d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
589d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
599d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
609d1b2987SEnric Balletbò i Serra 
619d1b2987SEnric Balletbò i Serra #define CONFIG_ENV_EEPROM_IS_ON_I2C
629d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
639d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
649d1b2987SEnric Balletbò i Serra 
659d1b2987SEnric Balletbò i Serra /* PMIC support */
669d1b2987SEnric Balletbò i Serra #define CONFIG_POWER_TPS65217
679d1b2987SEnric Balletbò i Serra #define CONFIG_POWER_TPS65910
689d1b2987SEnric Balletbò i Serra 
699d1b2987SEnric Balletbò i Serra /* SPL */
709d1b2987SEnric Balletbò i Serra 
719d1b2987SEnric Balletbò i Serra /* Bootcount using the RTC block */
729d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_BOOTCOUNT_BE
739d1b2987SEnric Balletbò i Serra 
74b432b1ebSFaiz Abbas #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
759d1b2987SEnric Balletbò i Serra /* Remove other SPL modes. */
769d1b2987SEnric Balletbò i Serra /* disable host part of MUSB in SPL */
779d1b2987SEnric Balletbò i Serra #undef CONFIG_MUSB_HOST
789d1b2987SEnric Balletbò i Serra /* disable EFI partitions and partition UUID support */
799d1b2987SEnric Balletbò i Serra #endif
809d1b2987SEnric Balletbò i Serra 
819d1b2987SEnric Balletbò i Serra #if defined(CONFIG_EMMC_BOOT)
829d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_MMC_ENV_DEV		1
839d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_MMC_ENV_PART		2
849d1b2987SEnric Balletbò i Serra #define CONFIG_ENV_OFFSET		0x0
859d1b2987SEnric Balletbò i Serra #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
869d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
879d1b2987SEnric Balletbò i Serra #endif
889d1b2987SEnric Balletbò i Serra 
899d1b2987SEnric Balletbò i Serra /* Network. */
909d1b2987SEnric Balletbò i Serra #define CONFIG_PHY_SMSC
919d1b2987SEnric Balletbò i Serra 
929d1b2987SEnric Balletbò i Serra #endif	/* ! __CONFIG_AM335X_SL50_H */
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