1 /* 2 * include/configs/alt.h 3 * This file is alt board configuration. 4 * 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #ifndef __ALT_H 11 #define __ALT_H 12 13 #undef DEBUG 14 #define CONFIG_R8A7794 15 #define CONFIG_RMOBILE_BOARD_STRING "Alt" 16 17 #include "rcar-gen2-common.h" 18 19 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) 20 #define CONFIG_SYS_TEXT_BASE 0x70000000 21 #else 22 #define CONFIG_SYS_TEXT_BASE 0xE6304000 23 #endif 24 25 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) 26 #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC 27 #else 28 #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 29 #endif 30 #define STACK_AREA_SIZE 0xC000 31 #define LOW_LEVEL_MERAM_STACK \ 32 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 33 34 /* MEMORY */ 35 #define RCAR_GEN2_SDRAM_BASE 0x40000000 36 #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 37 #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 38 39 /* SCIF */ 40 #define CONFIG_SCIF_CONSOLE 41 #define CONFIG_CONS_SCIF2 42 #define CONFIG_SCIF_USE_EXT_CLK 43 44 /* FLASH */ 45 #define CONFIG_SPI 46 #define CONFIG_SPI_FLASH_BAR 47 #define CONFIG_SH_QSPI 48 #define CONFIG_SPI_FLASH 49 #define CONFIG_SPI_FLASH_SPANSION 50 #define CONFIG_SPI_FLASH_QUAD 51 #define CONFIG_SYS_NO_FLASH 52 53 /* SH Ether */ 54 #define CONFIG_NET_MULTI 55 #define CONFIG_SH_ETHER 56 #define CONFIG_SH_ETHER_USE_PORT 0 57 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 58 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 59 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 60 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 61 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 62 #define CONFIG_PHYLIB 63 #define CONFIG_PHY_MICREL 64 #define CONFIG_BITBANGMII 65 #define CONFIG_BITBANGMII_MULTI 66 67 /* Board Clock */ 68 #define RMOBILE_XTAL_CLK 20000000u 69 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 70 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 71 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 72 #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) 73 #define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ 74 75 #define CONFIG_SYS_TMU_CLK_DIV 4 76 77 /* i2c */ 78 #define CONFIG_CMD_I2C 79 #define CONFIG_SYS_I2C 80 #define CONFIG_SYS_I2C_SH 81 #define CONFIG_SYS_I2C_SLAVE 0x7F 82 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 83 #define CONFIG_SYS_I2C_SH_SPEED0 400000 84 #define CONFIG_SYS_I2C_SH_SPEED1 400000 85 #define CONFIG_SYS_I2C_SH_SPEED2 400000 86 #define CONFIG_SH_I2C_DATA_HIGH 4 87 #define CONFIG_SH_I2C_DATA_LOW 5 88 #define CONFIG_SH_I2C_CLOCK 10000000 89 90 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 91 92 /* USB */ 93 #define CONFIG_USB_STORAGE 94 #define CONFIG_USB_EHCI 95 #define CONFIG_USB_EHCI_RMOBILE 96 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 97 98 /* MMCIF */ 99 #define CONFIG_MMC 100 #define CONFIG_GENERIC_MMC 101 #define CONFIG_CMD_MMC 102 103 #define CONFIG_SH_MMCIF 104 #define CONFIG_SH_MMCIF_ADDR 0xee200000 105 #define CONFIG_SH_MMCIF_CLK 48000000 106 107 /* Module stop status bits */ 108 /* INTC-RT */ 109 #define CONFIG_SMSTP0_ENA 0x00400000 110 /* MSIF */ 111 #define CONFIG_SMSTP2_ENA 0x00002000 112 /* INTC-SYS, IRQC */ 113 #define CONFIG_SMSTP4_ENA 0x00000180 114 /* SCIF2 */ 115 #define CONFIG_SMSTP7_ENA 0x00080000 116 117 #endif /* __ALT_H */ 118