1 /* 2 * include/configs/alt.h 3 * This file is alt board configuration. 4 * 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #ifndef __ALT_H 11 #define __ALT_H 12 13 #undef DEBUG 14 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt" 15 16 #include "rcar-gen2-common.h" 17 18 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 19 #define CONFIG_SYS_TEXT_BASE 0x70000000 20 #else 21 #define CONFIG_SYS_TEXT_BASE 0xE6304000 22 #endif 23 24 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 25 #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC 26 #else 27 #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 28 #endif 29 #define STACK_AREA_SIZE 0xC000 30 #define LOW_LEVEL_MERAM_STACK \ 31 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 32 33 /* MEMORY */ 34 #define RCAR_GEN2_SDRAM_BASE 0x40000000 35 #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 36 #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 37 38 /* SCIF */ 39 40 /* FLASH */ 41 #define CONFIG_SPI 42 #define CONFIG_SH_QSPI 43 #define CONFIG_SPI_FLASH_QUAD 44 45 /* SH Ether */ 46 #define CONFIG_SH_ETHER_USE_PORT 0 47 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 48 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 49 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 50 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 51 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 52 #define CONFIG_BITBANGMII 53 #define CONFIG_BITBANGMII_MULTI 54 55 /* Board Clock */ 56 #define RMOBILE_XTAL_CLK 20000000u 57 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 58 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 59 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 60 #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) 61 62 #define CONFIG_SYS_TMU_CLK_DIV 4 63 64 /* i2c */ 65 #define CONFIG_SYS_I2C 66 #define CONFIG_SYS_I2C_SH 67 #define CONFIG_SYS_I2C_SLAVE 0x7F 68 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 69 #define CONFIG_SYS_I2C_SH_SPEED0 400000 70 #define CONFIG_SYS_I2C_SH_SPEED1 400000 71 #define CONFIG_SYS_I2C_SH_SPEED2 400000 72 #define CONFIG_SH_I2C_DATA_HIGH 4 73 #define CONFIG_SH_I2C_DATA_LOW 5 74 #define CONFIG_SH_I2C_CLOCK 10000000 75 76 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 77 78 /* USB */ 79 #define CONFIG_USB_EHCI_RMOBILE 80 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 81 82 /* MMCIF */ 83 #define CONFIG_SH_MMCIF 84 #define CONFIG_SH_MMCIF_ADDR 0xee200000 85 #define CONFIG_SH_MMCIF_CLK 48000000 86 87 /* Module stop status bits */ 88 /* INTC-RT */ 89 #define CONFIG_SMSTP0_ENA 0x00400000 90 /* MSIF */ 91 #define CONFIG_SMSTP2_ENA 0x00002000 92 /* INTC-SYS, IRQC */ 93 #define CONFIG_SMSTP4_ENA 0x00000180 94 /* SCIF2 */ 95 #define CONFIG_SMSTP7_ENA 0x00080000 96 97 /* SDHI */ 98 #define CONFIG_SH_SDHI_FREQ 97500000 99 100 #endif /* __ALT_H */ 101