1*cff2f5f0SNobuhiro Iwamatsu /* 2*cff2f5f0SNobuhiro Iwamatsu * include/configs/alt.h 3*cff2f5f0SNobuhiro Iwamatsu * This file is alt board configuration. 4*cff2f5f0SNobuhiro Iwamatsu * 5*cff2f5f0SNobuhiro Iwamatsu * Copyright (C) 2014 Renesas Electronics Corporation 6*cff2f5f0SNobuhiro Iwamatsu * 7*cff2f5f0SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 8*cff2f5f0SNobuhiro Iwamatsu */ 9*cff2f5f0SNobuhiro Iwamatsu 10*cff2f5f0SNobuhiro Iwamatsu #ifndef __ALT_H 11*cff2f5f0SNobuhiro Iwamatsu #define __ALT_H 12*cff2f5f0SNobuhiro Iwamatsu 13*cff2f5f0SNobuhiro Iwamatsu #undef DEBUG 14*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_ARMV7 15*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_R8A7794 16*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_RMOBILE 17*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_RMOBILE_BOARD_STRING "Alt" 18*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_GPIO_PFC 19*cff2f5f0SNobuhiro Iwamatsu 20*cff2f5f0SNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 21*cff2f5f0SNobuhiro Iwamatsu 22*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_EDITENV 23*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_SAVEENV 24*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_MEMORY 25*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_DFL 26*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_SDRAM 27*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_RUN 28*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_LOADS 29*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_NET 30*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_MII 31*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_PING 32*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_DHCP 33*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_NFS 34*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_BOOTZ 35*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_SF 36*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_SPI 37*cff2f5f0SNobuhiro Iwamatsu 38*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0xE6304000 39*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_THUMB_BUILD 40*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_GENERIC_BOARD 41*cff2f5f0SNobuhiro Iwamatsu 42*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMDLINE_TAG 43*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SETUP_MEMORY_TAGS 44*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_INITRD_TAG 45*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMDLINE_EDITING 46*cff2f5f0SNobuhiro Iwamatsu 47*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_OF_LIBFDT 48*cff2f5f0SNobuhiro Iwamatsu #define BOARD_LATE_INIT 49*cff2f5f0SNobuhiro Iwamatsu 50*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_BAUDRATE 38400 51*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_BOOTDELAY 3 52*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_BOOTARGS "" 53*cff2f5f0SNobuhiro Iwamatsu 54*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_VERSION_VARIABLE 55*cff2f5f0SNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 56*cff2f5f0SNobuhiro Iwamatsu 57*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_ARCH_CPU_INIT 58*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_DISPLAY_CPUINFO 59*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_DISPLAY_BOARDINFO 60*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_BOARD_EARLY_INIT_F 61*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_TMU_TIMER 62*cff2f5f0SNobuhiro Iwamatsu 63*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 64*cff2f5f0SNobuhiro Iwamatsu #define STACK_AREA_SIZE 0xC000 65*cff2f5f0SNobuhiro Iwamatsu #define LOW_LEVEL_MERAM_STACK \ 66*cff2f5f0SNobuhiro Iwamatsu (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 67*cff2f5f0SNobuhiro Iwamatsu 68*cff2f5f0SNobuhiro Iwamatsu /* MEMORY */ 69*cff2f5f0SNobuhiro Iwamatsu #define ALT_SDRAM_BASE 0x40000000 70*cff2f5f0SNobuhiro Iwamatsu #define ALT_SDRAM_SIZE (1024u * 1024 * 1024) 71*cff2f5f0SNobuhiro Iwamatsu #define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 72*cff2f5f0SNobuhiro Iwamatsu 73*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_LONGHELP 74*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_CBSIZE 256 75*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_PBSIZE 256 76*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_MAXARGS 16 77*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_BARGSIZE 512 78*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } 79*cff2f5f0SNobuhiro Iwamatsu 80*cff2f5f0SNobuhiro Iwamatsu /* SCIF */ 81*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE 82*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CONS_SCIF2 83*cff2f5f0SNobuhiro Iwamatsu #undef CONFIG_SYS_CONSOLE_INFO_QUIET 84*cff2f5f0SNobuhiro Iwamatsu #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 85*cff2f5f0SNobuhiro Iwamatsu #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 86*cff2f5f0SNobuhiro Iwamatsu 87*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE) 88*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 89*cff2f5f0SNobuhiro Iwamatsu 504 * 1024 * 1024) 90*cff2f5f0SNobuhiro Iwamatsu #undef CONFIG_SYS_ALT_MEMTEST 91*cff2f5f0SNobuhiro Iwamatsu #undef CONFIG_SYS_MEMTEST_SCRATCH 92*cff2f5f0SNobuhiro Iwamatsu #undef CONFIG_SYS_LOADS_BAUD_CHANGE 93*cff2f5f0SNobuhiro Iwamatsu 94*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE) 95*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE) 96*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) 97*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_NR_DRAM_BANKS 1 98*cff2f5f0SNobuhiro Iwamatsu 99*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_BASE 0x00000000 100*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 101*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 102*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 103*cff2f5f0SNobuhiro Iwamatsu 104*cff2f5f0SNobuhiro Iwamatsu /* FLASH */ 105*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SPI 106*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SPI_FLASH_BAR 107*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_QSPI 108*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SPI_FLASH 109*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SPI_FLASH_SPANSION 110*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SPI_FLASH_QUAD 111*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_NO_FLASH 112*cff2f5f0SNobuhiro Iwamatsu 113*cff2f5f0SNobuhiro Iwamatsu /* ENV setting */ 114*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_ENV_IS_IN_SPI_FLASH 115*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_ENV_SECT_SIZE (256 * 1024) 116*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_ENV_ADDR 0xC0000 117*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 118*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 119*cff2f5f0SNobuhiro Iwamatsu 120*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_EXTRA_ENV_SETTINGS \ 121*cff2f5f0SNobuhiro Iwamatsu "bootm_low=0x40e00000\0" \ 122*cff2f5f0SNobuhiro Iwamatsu "bootm_size=0x100000\0" \ 123*cff2f5f0SNobuhiro Iwamatsu 124*cff2f5f0SNobuhiro Iwamatsu /* SH Ether */ 125*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_NET_MULTI 126*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER 127*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_USE_PORT 0 128*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_ADDR 0x1 129*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 130*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_CACHE_WRITEBACK 131*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_CACHE_INVALIDATE 132*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 133*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_PHYLIB 134*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_PHY_MICREL 135*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_BITBANGMII 136*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_BITBANGMII_MULTI 137*cff2f5f0SNobuhiro Iwamatsu 138*cff2f5f0SNobuhiro Iwamatsu /* Board Clock */ 139*cff2f5f0SNobuhiro Iwamatsu #define RMOBILE_XTAL_CLK 20000000u 140*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 141*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 142*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 143*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) 144*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ 145*cff2f5f0SNobuhiro Iwamatsu 146*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_TMU_CLK_DIV 4 147*cff2f5f0SNobuhiro Iwamatsu 148*cff2f5f0SNobuhiro Iwamatsu /* i2c */ 149*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_CMD_I2C 150*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C 151*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH 152*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SLAVE 0x7F 153*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 154*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 155*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_SPEED0 400000 156*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 157*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_SPEED1 400000 158*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 159*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_SPEED2 400000 160*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_HIGH 4 161*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_LOW 5 162*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_I2C_CLOCK 10000000 163*cff2f5f0SNobuhiro Iwamatsu 164*cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 165*cff2f5f0SNobuhiro Iwamatsu 166*cff2f5f0SNobuhiro Iwamatsu #endif /* __ALT_H */ 167