1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_USE_INTERRUPT 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_ARCH_MAP_SYSMEM 22 23 #define CONFIG_BOOTP_SEND_HOSTNAME 24 #define CONFIG_BOOTP_SERVERIP 25 26 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 27 #define CONFIG_MEM_REMAP 28 #endif 29 30 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 31 #ifdef CONFIG_OF_CONTROL 32 #undef CONFIG_OF_SEPARATE 33 #define CONFIG_OF_EMBED 34 #endif 35 #endif 36 37 /* 38 * Timer 39 */ 40 #define CONFIG_SYS_CLK_FREQ 39062500 41 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 42 43 /* 44 * Use Externel CLOCK or PCLK 45 */ 46 #undef CONFIG_FTRTC010_EXTCLK 47 48 #ifndef CONFIG_FTRTC010_EXTCLK 49 #define CONFIG_FTRTC010_PCLK 50 #endif 51 52 #ifdef CONFIG_FTRTC010_EXTCLK 53 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 54 #else 55 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 56 #endif 57 58 #define TIMER_LOAD_VAL 0xffffffff 59 60 /* 61 * Real Time Clock 62 */ 63 #define CONFIG_RTC_FTRTC010 64 65 /* 66 * Real Time Clock Divider 67 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 68 */ 69 #define OSC_5MHZ (5*1000000) 70 #define OSC_CLK (4*OSC_5MHZ) 71 #define RTC_DIV_COUNT (0.5) /* Why?? */ 72 73 /* 74 * Serial console configuration 75 */ 76 77 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 80 #ifndef CONFIG_DM_SERIAL 81 #define CONFIG_SYS_NS16550_REG_SIZE -4 82 #endif 83 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 84 85 /* 86 * Miscellaneous configurable options 87 */ 88 89 /* 90 * Size of malloc() pool 91 */ 92 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 93 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 94 95 /* 96 * AHB Controller configuration 97 */ 98 #define CONFIG_FTAHBC020S 99 100 #ifdef CONFIG_FTAHBC020S 101 #include <faraday/ftahbc020s.h> 102 103 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 104 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 105 106 /* 107 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 108 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 109 * in C language. 110 */ 111 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 112 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 113 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 114 #endif 115 116 /* 117 * Watchdog 118 */ 119 #define CONFIG_FTWDT010_WATCHDOG 120 121 /* 122 * PMU Power controller configuration 123 */ 124 #define CONFIG_PMU 125 #define CONFIG_FTPMU010_POWER 126 127 #ifdef CONFIG_FTPMU010_POWER 128 #include <faraday/ftpmu010.h> 129 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 130 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 131 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 132 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 133 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 134 FTPMU010_SDRAMHTC_CKE_DCSR | \ 135 FTPMU010_SDRAMHTC_DQM_DCSR | \ 136 FTPMU010_SDRAMHTC_SDCLK_DCSR) 137 #endif 138 139 /* 140 * SDRAM controller configuration 141 */ 142 #define CONFIG_FTSDMC021 143 144 #ifdef CONFIG_FTSDMC021 145 #include <faraday/ftsdmc021.h> 146 147 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 148 FTSDMC021_TP1_TRP(1) | \ 149 FTSDMC021_TP1_TRCD(1) | \ 150 FTSDMC021_TP1_TRF(3) | \ 151 FTSDMC021_TP1_TWR(1) | \ 152 FTSDMC021_TP1_TCL(2)) 153 154 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 155 FTSDMC021_TP2_INI_REFT(8) | \ 156 FTSDMC021_TP2_REF_INTV(0x180)) 157 158 /* 159 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 160 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 161 * C language. 162 */ 163 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 164 FTSDMC021_CR1_DSZ(3) | \ 165 FTSDMC021_CR1_MBW(2) | \ 166 FTSDMC021_CR1_BNKSIZE(6)) 167 168 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 169 FTSDMC021_CR2_IREF | \ 170 FTSDMC021_CR2_ISMR) 171 172 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 173 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 174 CONFIG_SYS_FTSDMC021_BANK0_BASE) 175 176 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 177 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 178 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 179 CONFIG_SYS_FTSDMC021_BANK1_BASE) 180 #endif 181 182 /* 183 * Physical Memory Map 184 */ 185 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 186 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 187 #else 188 #ifdef CONFIG_MEM_REMAP 189 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 190 #else 191 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 192 #endif 193 #endif 194 195 #define PHYS_SDRAM_1 \ 196 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 197 198 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 199 200 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 201 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 202 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 203 #else 204 #ifdef CONFIG_MEM_REMAP 205 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 206 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 207 #else 208 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 209 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 210 #endif 211 #endif 212 213 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 214 215 #ifdef CONFIG_MEM_REMAP 216 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 217 GENERATED_GBL_DATA_SIZE) 218 #else 219 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 220 GENERATED_GBL_DATA_SIZE) 221 #endif /* CONFIG_MEM_REMAP */ 222 223 /* 224 * Load address and memory test area should agree with 225 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 226 */ 227 #define CONFIG_SYS_LOAD_ADDR 0x300000 228 229 /* memtest works on 63 MB in DRAM */ 230 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 231 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 232 233 /* 234 * Static memory controller configuration 235 */ 236 #define CONFIG_FTSMC020 237 238 #ifdef CONFIG_FTSMC020 239 #include <faraday/ftsmc020.h> 240 241 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 242 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 243 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 244 } 245 246 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 247 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 248 FTSMC020_BANK_SIZE_32M | \ 249 FTSMC020_BANK_MBW_32) 250 251 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 252 FTSMC020_TPR_AST(1) | \ 253 FTSMC020_TPR_CTW(1) | \ 254 FTSMC020_TPR_ATI(1) | \ 255 FTSMC020_TPR_AT2(1) | \ 256 FTSMC020_TPR_WTC(1) | \ 257 FTSMC020_TPR_AHT(1) | \ 258 FTSMC020_TPR_TRNA(1)) 259 #endif 260 261 /* 262 * FLASH on ADP_AG101P is connected to BANK0 263 * Just disalbe the other BANK to avoid detection error. 264 */ 265 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 266 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 267 FTSMC020_BANK_SIZE_32M | \ 268 FTSMC020_BANK_MBW_32) 269 270 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 271 FTSMC020_TPR_CTW(3) | \ 272 FTSMC020_TPR_ATI(0xf) | \ 273 FTSMC020_TPR_AT2(3) | \ 274 FTSMC020_TPR_WTC(3) | \ 275 FTSMC020_TPR_AHT(3) | \ 276 FTSMC020_TPR_TRNA(0xf)) 277 278 #define FTSMC020_BANK1_CONFIG (0x00) 279 #define FTSMC020_BANK1_TIMING (0x00) 280 #endif /* CONFIG_FTSMC020 */ 281 282 /* 283 * FLASH and environment organization 284 */ 285 /* use CFI framework */ 286 #define CONFIG_SYS_FLASH_CFI 287 #define CONFIG_FLASH_CFI_DRIVER 288 289 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 290 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 291 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 292 293 /* support JEDEC */ 294 295 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 296 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 297 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 298 #else 299 #ifdef CONFIG_MEM_REMAP 300 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 301 #else 302 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 303 #endif 304 #endif /* CONFIG_MEM_REMAP */ 305 306 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 307 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 308 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 309 310 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 311 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 312 313 /* max number of memory banks */ 314 /* 315 * There are 4 banks supported for this Controller, 316 * but we have only 1 bank connected to flash on board 317 */ 318 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 319 #define CONFIG_SYS_MAX_FLASH_BANKS 1 320 #endif 321 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 322 323 /* max number of sectors on one chip */ 324 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 325 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 326 #define CONFIG_SYS_MAX_FLASH_SECT 512 327 328 /* environments */ 329 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 330 #define CONFIG_ENV_SIZE 8192 331 #define CONFIG_ENV_OVERWRITE 332 333 /* 334 * For booting Linux, the board info and command line data 335 * have to be in the first 16 MB of memory, since this is 336 * the maximum mapped by the Linux kernel during initialization. 337 */ 338 339 /* Initial Memory map for Linux*/ 340 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 341 /* Increase max gunzip size */ 342 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 343 344 #endif /* __CONFIG_H */ 345