1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #define CONFIG_SYS_GENERIC_GLOBAL_DATA 24 25 /* 26 * Definitions related to passing arguments to kernel. 27 */ 28 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 29 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 30 #define CONFIG_INITRD_TAG /* send initrd params */ 31 32 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 33 #define CONFIG_MEM_REMAP 34 #endif 35 36 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 37 #define CONFIG_SYS_TEXT_BASE 0x00500000 38 #else 39 #ifdef CONFIG_MEM_REMAP 40 #define CONFIG_SYS_TEXT_BASE 0x80000000 41 #else 42 #define CONFIG_SYS_TEXT_BASE 0x00000000 43 #endif 44 #endif 45 46 /* 47 * Timer 48 */ 49 #define CONFIG_SYS_CLK_FREQ 39062500 50 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 51 52 /* 53 * Use Externel CLOCK or PCLK 54 */ 55 #undef CONFIG_FTRTC010_EXTCLK 56 57 #ifndef CONFIG_FTRTC010_EXTCLK 58 #define CONFIG_FTRTC010_PCLK 59 #endif 60 61 #ifdef CONFIG_FTRTC010_EXTCLK 62 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 63 #else 64 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 65 #endif 66 67 #define TIMER_LOAD_VAL 0xffffffff 68 69 /* 70 * Real Time Clock 71 */ 72 #define CONFIG_RTC_FTRTC010 73 74 /* 75 * Real Time Clock Divider 76 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 77 */ 78 #define OSC_5MHZ (5*1000000) 79 #define OSC_CLK (4*OSC_5MHZ) 80 #define RTC_DIV_COUNT (0.5) /* Why?? */ 81 82 /* 83 * Serial console configuration 84 */ 85 86 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 87 #define CONFIG_CONS_INDEX 1 88 #define CONFIG_SYS_NS16550_SERIAL 89 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 90 #define CONFIG_SYS_NS16550_REG_SIZE -4 91 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 92 93 /* 94 * Ethernet 95 */ 96 #define CONFIG_FTMAC100 97 98 99 /* 100 * SD (MMC) controller 101 */ 102 #define CONFIG_FTSDC010 103 #define CONFIG_FTSDC010_NUMBER 1 104 #define CONFIG_FTSDC010_SDIO 105 106 /* 107 * Command line configuration. 108 */ 109 #define CONFIG_CMD_DATE 110 111 /* 112 * Miscellaneous configurable options 113 */ 114 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 115 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 116 117 /* Print Buffer Size */ 118 #define CONFIG_SYS_PBSIZE \ 119 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 120 121 /* max number of command args */ 122 #define CONFIG_SYS_MAXARGS 16 123 124 /* Boot Argument Buffer Size */ 125 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 126 127 /* 128 * Size of malloc() pool 129 */ 130 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 131 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 132 133 /* 134 * AHB Controller configuration 135 */ 136 #define CONFIG_FTAHBC020S 137 138 #ifdef CONFIG_FTAHBC020S 139 #include <faraday/ftahbc020s.h> 140 141 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 142 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 143 144 /* 145 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 146 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 147 * in C language. 148 */ 149 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 150 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 151 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 152 #endif 153 154 /* 155 * Watchdog 156 */ 157 #define CONFIG_FTWDT010_WATCHDOG 158 159 /* 160 * PMU Power controller configuration 161 */ 162 #define CONFIG_PMU 163 #define CONFIG_FTPMU010_POWER 164 165 #ifdef CONFIG_FTPMU010_POWER 166 #include <faraday/ftpmu010.h> 167 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 168 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 169 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 170 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 171 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 172 FTPMU010_SDRAMHTC_CKE_DCSR | \ 173 FTPMU010_SDRAMHTC_DQM_DCSR | \ 174 FTPMU010_SDRAMHTC_SDCLK_DCSR) 175 #endif 176 177 /* 178 * SDRAM controller configuration 179 */ 180 #define CONFIG_FTSDMC021 181 182 #ifdef CONFIG_FTSDMC021 183 #include <faraday/ftsdmc021.h> 184 185 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 186 FTSDMC021_TP1_TRP(1) | \ 187 FTSDMC021_TP1_TRCD(1) | \ 188 FTSDMC021_TP1_TRF(3) | \ 189 FTSDMC021_TP1_TWR(1) | \ 190 FTSDMC021_TP1_TCL(2)) 191 192 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 193 FTSDMC021_TP2_INI_REFT(8) | \ 194 FTSDMC021_TP2_REF_INTV(0x180)) 195 196 /* 197 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 198 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 199 * C language. 200 */ 201 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 202 FTSDMC021_CR1_DSZ(3) | \ 203 FTSDMC021_CR1_MBW(2) | \ 204 FTSDMC021_CR1_BNKSIZE(6)) 205 206 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 207 FTSDMC021_CR2_IREF | \ 208 FTSDMC021_CR2_ISMR) 209 210 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 211 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 212 CONFIG_SYS_FTSDMC021_BANK0_BASE) 213 214 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 215 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 216 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 217 CONFIG_SYS_FTSDMC021_BANK1_BASE) 218 #endif 219 220 /* 221 * Physical Memory Map 222 */ 223 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 224 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 225 #else 226 #ifdef CONFIG_MEM_REMAP 227 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 228 #else 229 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 230 #endif 231 #endif 232 233 #define PHYS_SDRAM_1 \ 234 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 235 236 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 237 238 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 239 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 240 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 241 #else 242 #ifdef CONFIG_MEM_REMAP 243 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 244 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 245 #else 246 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 247 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 248 #endif 249 #endif 250 251 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 252 253 #ifdef CONFIG_MEM_REMAP 254 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 255 GENERATED_GBL_DATA_SIZE) 256 #else 257 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 258 GENERATED_GBL_DATA_SIZE) 259 #endif /* CONFIG_MEM_REMAP */ 260 261 /* 262 * Load address and memory test area should agree with 263 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 264 */ 265 #define CONFIG_SYS_LOAD_ADDR 0x300000 266 267 /* memtest works on 63 MB in DRAM */ 268 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 269 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 270 271 /* 272 * Static memory controller configuration 273 */ 274 #define CONFIG_FTSMC020 275 276 #ifdef CONFIG_FTSMC020 277 #include <faraday/ftsmc020.h> 278 279 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 280 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 281 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 282 } 283 284 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 285 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 286 FTSMC020_BANK_SIZE_32M | \ 287 FTSMC020_BANK_MBW_32) 288 289 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 290 FTSMC020_TPR_AST(1) | \ 291 FTSMC020_TPR_CTW(1) | \ 292 FTSMC020_TPR_ATI(1) | \ 293 FTSMC020_TPR_AT2(1) | \ 294 FTSMC020_TPR_WTC(1) | \ 295 FTSMC020_TPR_AHT(1) | \ 296 FTSMC020_TPR_TRNA(1)) 297 #endif 298 299 /* 300 * FLASH on ADP_AG101P is connected to BANK0 301 * Just disalbe the other BANK to avoid detection error. 302 */ 303 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 304 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 305 FTSMC020_BANK_SIZE_32M | \ 306 FTSMC020_BANK_MBW_32) 307 308 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 309 FTSMC020_TPR_CTW(3) | \ 310 FTSMC020_TPR_ATI(0xf) | \ 311 FTSMC020_TPR_AT2(3) | \ 312 FTSMC020_TPR_WTC(3) | \ 313 FTSMC020_TPR_AHT(3) | \ 314 FTSMC020_TPR_TRNA(0xf)) 315 316 #define FTSMC020_BANK1_CONFIG (0x00) 317 #define FTSMC020_BANK1_TIMING (0x00) 318 #endif /* CONFIG_FTSMC020 */ 319 320 /* 321 * FLASH and environment organization 322 */ 323 /* use CFI framework */ 324 #define CONFIG_SYS_FLASH_CFI 325 #define CONFIG_FLASH_CFI_DRIVER 326 327 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 328 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 329 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 330 331 /* support JEDEC */ 332 333 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 334 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 335 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 336 #else 337 #ifdef CONFIG_MEM_REMAP 338 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 339 #else 340 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 341 #endif 342 #endif /* CONFIG_MEM_REMAP */ 343 344 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 345 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 346 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 347 348 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 349 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 350 351 /* max number of memory banks */ 352 /* 353 * There are 4 banks supported for this Controller, 354 * but we have only 1 bank connected to flash on board 355 */ 356 #define CONFIG_SYS_MAX_FLASH_BANKS 1 357 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 358 359 /* max number of sectors on one chip */ 360 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 361 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 362 #define CONFIG_SYS_MAX_FLASH_SECT 512 363 364 /* environments */ 365 #define CONFIG_ENV_IS_IN_FLASH 366 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 367 #define CONFIG_ENV_SIZE 8192 368 #define CONFIG_ENV_OVERWRITE 369 370 #endif /* __CONFIG_H */ 371